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Locum Asic Rtl Design Engineer Jobs in Mountain View, CA

CYNET SYSTEMS

ASIC/RTL Design Engineer 2

San Jose, CA · On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Google

RTL Design Engineer, TPU and ML

Sunnyvale, CA · On-site

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

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All JobsLocum Asic Rtl Design Engineer JobsLocum Asic Rtl Design Engineer Jobs in Mountain View, CA

Locum Asic Rtl Design Engineer information

See Mountain View, CA salary details

$110.9K

$177.2K

$238.3K

How much do locum asic rtl design engineer jobs pay per year?

As of Aug 13, 2026, the average yearly pay for locum asic rtl design engineer in Mountain View, CA is $177,183.00, according to ZipRecruiter salary data. Most workers in this role earn between $155,100.00 and $212,300.00 per year, depending on experience, location, and employer.

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Mountain View, CA?

The most popular types of Asic Rtl Design Engineer jobs in Mountain View, CA are:

What are popular job titles related to Locum Asic Rtl Design Engineer jobs in Mountain View, CA?

For Locum Asic Rtl Design Engineer jobs in Mountain View, CA, the most frequently searched job titles are:

What job categories do people searching Locum Asic Rtl Design Engineer jobs in Mountain View, CA look for?

The top searched job categories for Locum Asic Rtl Design Engineer jobs in Mountain View, CA are:

What cities near Mountain View, CA are hiring for Locum Asic Rtl Design Engineer jobs?

Cities near Mountain View, CA with the most Locum Asic Rtl Design Engineer job openings:

Locum Asic Rtl Design Engineer jobs near you
Infographic showing various Locum Asic Rtl Design Engineer job openings in Mountain View, CA as of August 2026, with employment types broken down into 25% Internship, and 75% Contract. Highlights an 100% In-person job distribution, with an average salary of $177,183 per year, or $85.2 per hour.

Lead ASIC RTL Design Engineer

4 Staffing Corp

San Francisco, CA • On-site, Remote

Full-time

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

About the job Lead ASIC RTL Design Engineer
Lead ASIC RTL Design Engineer - Remote (U.S.) - No visa sponsorship
Role Summary
Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.
Core Responsibilities
Architecture & RTL Development

  • Define microarchitecture for complex subsystems and document design specifications
  • Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
  • Incorporate assertions and design-for-debug features within RTL
Design Ownership & Implementation
  • Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
  • Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
  • Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks
High-Speed Interfaces & Memory Systems
  • Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
  • Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
  • Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality
Engineering Processes & Tooling
  • Establish and maintain RTL design standards, reusable components, and signoff criteria
  • Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)
Collaboration & System Integration
  • Partner with verification teams on test planning, coverage goals, and model alignment
  • Work with architecture and performance engineering to validate design intent against system-level expectations
  • Support silicon bring-up, debugging, and downstream customer or system integration efforts
Technical Leadership
  • Mentor less experienced engineers and provide guidance on design best practices
  • Lead design reviews and help drive key technical decisions across teams
  • Advocate for scalable, efficient, and high-quality engineering solutions
Basic Qualifications
  • Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
  • 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
  • Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
  • Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
  • Hands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
  • Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
  • Strong communication skills with the ability to lead technical discussions and document designs clearly
Preferred Experience
  • Exposure to AI/ML hardware or high-performance compute architectures
  • Knowledge of formal verification techniques and assertion-based design
  • Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
  • Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
  • Understanding of modern processor subsystems, coherence models, or custom tool flows

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