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Contractual Asic Rtl Design Engineer Jobs in Mountain View, CA

ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data processing chip. Micro-architecture definition, writing micro-architecture specifications. Write ...

New

ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data processing chip. Micro-architecture definition, writing micro-architecture specifications. Write ...

New

Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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Contractual Asic Rtl Design Engineer information

See Mountain View, CA salary details

$110.9K

$177.2K

$238.3K

How much do contractual asic rtl design engineer jobs pay per year?

As of Aug 30, 2026, the average yearly pay for contractual asic rtl design engineer in Mountain View, CA is $177,183.00, according to ZipRecruiter salary data. Most workers in this role earn between $155,100.00 and $212,300.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Mountain View, CA?

The most popular types of Asic Rtl Design Engineer jobs in Mountain View, CA are:

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For Contractual Asic Rtl Design Engineer jobs in Mountain View, CA, the most frequently searched job titles are:

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The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Mountain View, CA are:

What cities near Mountain View, CA are hiring for Contractual Asic Rtl Design Engineer jobs?

Cities near Mountain View, CA with the most Contractual Asic Rtl Design Engineer job openings:

ASIC RTL Design Engineer

Santa Clara, CA • On-site

InterSources
Recruiting and Staffing Services • 51 - 200 employees

Full-time

This job post has expired today. Applications are no longer accepted.


Job description

ASIC RTL Design Engineer

Responsible for microarchitecture and RTL design of high performance data processing chip. Micro-architecture definition, writing micro-architecture specifications. Write high performance and low power Verilog RTL, synthesis and timing closure. Collaborate with our verification team to verify the correctness of your unit. Work with implementation to achieve your timing, area, performance and power goals. Identify performance bottlenecks and optimize system performance.

What we are looking for: Member of our core team, responsible for crafting and timely delivery of a specific units. A strong background in computer architecture is highly desirable. Strong communication and interpersonal skills are required working with global team. More than 5 years of experience in high performance Verilog RTL designs. Verilog expertise and deep understanding of ASIC design flow. Expertise in Verilog RTL design, logic synthesis, prototyping, and timing closure. Bachelor or Master Degree in Electrical Engineering or Computer Science. Learn new technologies and apply the knowledge quickly. Able to meet project milestones and deadlines.


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About InterSources

Sourced by ZipRecruiter

In 2007, Our journey began as pioneers in the realm of technology and security. Since then, InterSources Inc. has evolved into a trusted partner, leading the way in Cloud Security, Cybersecurity, PLG Consulting, Digital Transformation, and Professional Services. With a rich history of excellence and a forward-thinking approach, we continue to secure your digital future and drive innovation. Explore our legacy of success and discover the possibilities that lie ahead.

Industry

Recruiting and staffing services

Company size

51 - 200 Employees

Headquarters location

Fremont, CA, US

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