1

Contractual Asic Rtl Design Engineer Jobs in Galt, CA

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...

HBM SoC RTL Design Engineer

Folsom, CA · On-site

$121K - $247K/yr

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...

HBM SoC RTL Design Engineer

Folsom, CA · On-site

$146K - $297K/yr

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...

As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...

Join Solidigm's visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help ... Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL ...

Join Solidigm's visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help ... Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL ...

... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design ... Stakeholder EngagementCommunicate effectively with senior engineering leaders, product teams, and ...

... and ASIC/Foundry products. • Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams. • Manage schedule ...

HBM SoC Physical Design Engineer

Folsom, CA · On-site

$145K - $149K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...

next page

Showing results 1-20

Contractual Asic Rtl Design Engineer information

See Galt, CA salary details

$97.4K

$155.7K

$209.4K

How much do contractual asic rtl design engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for contractual asic rtl design engineer in Galt, CA is $155,689.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,300.00 and $186,600.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Galt, CA?

The most popular types of Asic Rtl Design Engineer jobs in Galt, CA are:

What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Galt, CA look for?

The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Galt, CA are:

What cities near Galt, CA are hiring for Contractual Asic Rtl Design Engineer jobs?

Cities near Galt, CA with the most Contractual Asic Rtl Design Engineer job openings:

Senior RTL Design Engineer -- HBM SoC

1000 Micron Technology, Inc.

Folsom, CA • On-site

$200 - $250/hr

Other

Posted 5 days ago


Job description

1000 Micron Technology, Inc. is seeking a SoC Design Engineer to design and develop next-generation HBM SoC logic die. You will work with architecture, verification, and product teams to ensure high-performance solutions meet various targets.

The role requires collaboration on RTL design, integration of IPs, and participation in the integration activities. A minimum of 10 years of experience and a degree in electrical or computer engineering are required.

A strong knowledge of SystemVerilog/Verilog and EDA tools is essential, with a salary range of $146,000.00 – $297,000.00 per year.

#J-18808-Ljbffr