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Locum Asic Rtl Design Engineer Jobs (NOW HIRING)

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Principal RTL Design Engineer

Austin, TX · On-site

$180K - $255K/yr

B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...

Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...

Sr Digital Design Engineer

Boise, ID · On-site

$129K/yr

Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...

Showing results 21-40

Locum Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do locum asic rtl design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for locum asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

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Infographic showing various Locum Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ASIC RTL/SoC Design Engineer

Fremont, CA • On-site

TetraMem INC
Computer and Peripheral Equipment Manufacturing • 11 - 50 employees

Full-time

Medical, Retirement, PTO

Re-posted 4 days ago


Job description

Company Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description
  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.

  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.

  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.

  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.

  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.

  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.

  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.

  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.

  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.

  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.

Qualifications
  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

  • Experience with Verilog and system Verilog

  • Experience with VCS, Verdi or other industry standard tools

  • Experience with pre-layout simulation and post-layout simulation

  • Understanding of the design flow. Ability to work with the backend team

  • Familiarity with AMBA APB AXI Protocol

  • Familiarity with RISC/Arm or other core architectures

  • Ability to create innovative architecture and solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems

  • Working knowledge of SoC architecture such as CPU, GPU or accelerators

  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Additional Information

All your information will be kept confidential according to EEO guidelines.