ZipRecruiter

Log In

1

Internship Asic Rtl Design Engineer Jobs (NOW HIRING)

Nutanix

ASIC Design Engineer

San Diego, CA · On-site

Contribute to ASIC development activities including RTL design, static timing analysis, timing ... Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.Strong ...

Google

RTL Design Engineer, TPU and ML

Sunnyvale, CA · On-site

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

Waymo

ML ASIC Design Engineer

Mountain View, NY · Hybrid

... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...

Synopsys

ASIC Digital Design, Architect - 18388

Austin, TX · On-site

$181K - $271K/yr

Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Sivaltech

RTL Engineer (Ethernet)

San Francisco, CA · On-site

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...

New

Teradyne

RTL Design Engineer

Reading, MA · On-site

$123K - $196K/yr

... ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation ... Responsibilities * Develop specifications, micro‑architecture, and RTL design of ...

previous page

Showing results 41-60

All JobsInternship JobsEngineering JobsEngineers JobsInternship Asic Rtl Design Engineer Jobs

Internship Asic Rtl Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do internship asic rtl design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for internship asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

More about Internship Asic Rtl Design Engineer jobs

What cities are hiring for Internship Asic Rtl Design Engineer jobs?

Cities with the most Internship Asic Rtl Design Engineer job openings:

What are the most commonly searched types of Asic Rtl Design Engineer jobs?

The most popular types of Asic Rtl Design Engineer jobs are:

What states have the most Internship Asic Rtl Design Engineer jobs?

States with the most job openings for Internship Asic Rtl Design Engineer jobs include:

What are popular job titles related to Internship Asic Rtl Design Engineer jobs?

For Internship Asic Rtl Design Engineer jobs, the most frequently searched job titles are:

Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Senior ASIC Design Engineer

San Francisco, CA • On-site

Ethan Alexander Group
Recruiting and Staffing Services • 1 - 10 employees
Learn more about Ethan Alexander Groupexternal

Full-time

Re-posted 14 days ago

Job description

ASIC Design Engineer


Responsibilities:


  • Define and bring up FPGA platforms for pre-silicon validation and software development
  • Map ASIC RTL to FGPA while minimizing code base differences
  • Create and execute test plans for validating SoC functionality and performance
  • Resolve challenging system level issues that span multiple disciplines
  • Design logic starting from specification or high level feature description


Requirements:


  • Minimum of 5 years of relevant experience.
  • Scripting or programming experience in Python or C/C++
  • Ability to write and analyze the completeness of constraints
  • Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters
  • Strong analytical and debugging skills
  • BS in Electrical Engineering or equivalent required, MS preferred


Nice to Have:


  • Familiarity with Xilinx FPGA’s and Vivado tool chain
  • Experience with validating and debugging low-power wireless systems
  • Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)
  • Knowledge of wireless protocols (e.g. Bluetooth Low Energy)