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Internship Asic Rtl Design Engineer Jobs in Ohio

Niobiummicrosystems

ASIC Physical Design Lead

Dayton, OH · On-site

$150 - $200/hr

In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power ... Mentor, coach, and guide engineers in methodology, debug, and best practices. * Champion continuous ...

Niobiummicrosystems

ASIC Physical Design Lead

Columbus, OH · On-site

$150 - $200/hr

In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power ... Mentor, coach, and guide engineers in methodology, debug, and best practices. * Champion continuous ...

Battelle

ASIC/FPGA/Hardware Engineer

Columbus, OH · On-site

... ASIC/FPGA/Hardware Engineer to work in our Columbus, Ohio location. "From Silicon to Systems" - We ... Perform and support digital circuit analysis throughout various stages of the design lifecycle (RTL ...

Afference

ASIC Engineer

Cleveland, OH · On-site

$116K - $174K/yr

Help shape the design and development of ASIC chips under the guidance of senior engineers and leadership. * Collaborate with product teams to align ASIC design efforts with customer requirements.

GDR Defense

Bridge Design Engineer

Loveland, OH · On-site

Bridge Design Engineer Location: Loveland, OH Salary: $75,000 Annually Position Type: Full-Time ... Experience with structural or bridge design (internship or professional). * Exposure to hydraulic ...

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Internship Asic Rtl Design Engineer information

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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ASIC Physical Design Lead

Niobiummicrosystems

Dayton, OH • On-site

$150 - $200/hr

Other

Medical, Dental, Vision, Retirement

Posted 6 days ago

Key responsibilities

  • Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.

  • Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.

  • Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.

Job description

About Niobium

At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner of government research teams and commercial customers whose solutions require lower power, higher efficiency, and proven security.

Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.

About This Role

We are seeking a highly experienced ASIC Physical Design to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 8+ years of hands‑on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally.

In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power‑efficient silicon across cutting edge technology nodes.

Responsibilities End-to-End Physical Implementation Leadership
  • Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.
  • Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow.
Floorplanning & SoC Integration
  • Architect and execute floorplanning strategies for large, hierarchical SoCs, including:
    • IP integration and macro placement
    • Physical partitioning and hierarchy definition
    • Power grid architecture and clock distribution topology
    • DIE size, aspect ratio, and physical constraints
  • Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.
Place & Route + Timing Closure
  • Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys).
  • Drive timing convergence across corners, modes, voltage domains, and operating conditions.
  • Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity.
Clocking, Power, and Sign-Off
  • Implement CTS and drive skew, latency, and clock power optimization.
  • Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC).
  • Integrate and validate low power methodologies, including UPF/CPF flows.
Cross-Functional Collaboration & Quality Ownership
  • Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.
  • Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.
  • Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout.
Leadership & Mentorship
  • Provide technical leadership to a team of junior and mid-level physical designers.
  • Mentor, coach, and guide engineers in methodology, debug, and best practices.
  • Champion continuous improvement across flows, scripts, and design methodology.
Key Qualifications Education
  • BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. (Advanced degree preferred for leadership roles.)
Required Technical Expertise
  • 8+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape‑outs at advanced technology nodes (16nm -> 3nm preferred).
  • Deep expertise in:
    • Floorplanning
    • Place & Route
    • CTS
    • STA/Timing Closure
    • Physical verification & sign-off
    • Low power design and UPF
  • Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
  • Solid understanding of RTL-to-GDS flows, design architecture trade‑offs, and SoC integration complexities.
  • Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.
Required General Skills
  • Strong communication skills—able to articulate technical decisions across cross-functional teams.
  • Highly motivated, proactive, and able to operate effectively in a distributed team environment.
  • Comfortable owning schedules, deliverables, and quality in a fast‑moving development cycle.
  • Exceptional analytical, debugging, and problem‑solving skills with a meticulous attention to detail.
Location

Niobium is headquartered in Columbus, Ohio with additional locations in Fayetteville, Arkansas, Portland, Oregon, and Dayton, Ohio. We will not be limited by geography for the right candidate.

Benefits

Niobium offers a highly competitive benefits program to support employees and their families, including:

  • Competitive salaries
  • Equity in the form of Incentive Stock Options (ISO)
  • Employer paid medical insurance plan
  • Health Savings Account (HSA) with employer contributions
  • Dental and vision reimbursement account (HRA)
  • 401(k) retirement plan with employer match
  • Flexible work location with remote options
  • Flexible time off
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