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Internship Asic Rtl Design Engineer Jobs in Cincinnati, OH

GDR Defense

Bridge Design Engineer

Loveland, OH · On-site

Bridge Design Engineer Location: Loveland, OH Salary: $75,000 Annually Position Type: Full-Time ... Experience with structural or bridge design (internship or professional). * Exposure to hydraulic ...

SSI Fabricated

Mechanical Design Engineer

Middletown, OH

$72K - $97K/yr

Minimum of 3 years of experience in piping design, PVF, or related equipment engineering such as pumps, valves, or fluid system components; new graduates with relevant co-op or internship experience ...

Apex Systems

CAD/ Mechanical Engineer 1

Hebron, KY · On-site

$73K - $99K/yr

Job#: 3040368 CAD Technician Location: Hebron, Kentucky (Onsite) Role Overview We are seeking a ... Internship or co-op experience in engineering, manufacturing, or construction. * Exposure to ...

RennickBarrett Recruiting, INC

FPGA Engineer

Cincinnati, OH · On-site

$124K - $160K/yr

ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...

Benesch

Bridge Design Internship

Cincinnati, OH · On-site

This role will involve applying structural engineering techniques to support the design and ... This allows you to benefit from mentorship by professionals in the office during your internship at ...

EndoSec LLC

FPGA Engineer

Cincinnati, OH

$124K - $160K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Cincinnati, OH

Internship Asic Rtl Design Engineer information

See Cincinnati, OH salary details

$90.2K

$144.1K

$193.8K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for internship asic rtl design engineer in Cincinnati, OH is $144,109.00, according to ZipRecruiter salary data. Most workers in this role earn between $126,200.00 and $172,700.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Cincinnati, OH as of August 2026, with employment types broken down into 52% Full Time, 11% Part Time, and 37% Contract. Highlights an 100% In-person job distribution, with an average salary of $144,109 per year, or $69.3 per hour.

VDHL Design Engineer

Wright Technical Services

Cincinnati, OH • On-site

Full-time

Posted 19 days ago

Job description

VHDL Design Engineer

All candidates must be eligible to obtain a United States Security Clearance
Candidates must be able to commute to Cincinnati, Ohio on a regular basis if not local

The FPGA/ASIC Firmware Engineer is expected to design, architect, and implement waveforms and digital signal processing (DSP) algorithms using VHDL or Verilog targeting software defined radio (SDR) hardware. Firmware development is applied to high complexity and high throughput implementations with a focus on VHDL, code re-use, fixed-point modeling, low power design, system integration, test automation, FPGA/ASIC IP Core development and product test/support while leveraging advancements in systems-on-chip (SoCs), synthesis tools and SDR hardware. We are looking for individuals who have demonstrated abilities in innovative thinking and versatility in their jobs with experience in the following: FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and proposal, report and system/product specification development. The individual will work within a team environment to achieve high efficiency in solving our customer's formidable challenges and meeting our customer's requirements objectives.

Roles and Responsibilities

  • Demonstrated leadership skills/experience in digital design engineering, HDL coding, implementation of waveforms/modems and digital signal processing, performance/test analysis and technical team leadership.
  • Implementation of waveforms/algorithms in VHDL (preferred) or Verilog.
  • Experienced with lab and field testing, test equipment such as signal generators, spectrum analyzers, and digital logic analyzers.
  • Familiarity with signal processing systems, terrestrial/airborne/satellite transmitter and receiver design including acquisition, tracking and demodulation, MATLAB, C/C++, synthesis, verification/acceptance testing.
  • Individuals with a background developing solutions for military/DoD customers is plus.
  • Provide concise explanation and design documentation of developed firmware implementation to enable team members to support system integration.
  • Identification, development and implementation of FPGA/ASIC IP Cores.
  • Deliver effective briefings and to work efficiently in a multidisciplinary team environment.
  • Travel to support events such as customer site support, training seminar, proposals.
  • Proactively ensure a safe work environment and adhere to company policies and procedures.

Qualifications

  • Bachelor's degree or Master's degree, preferable with work experience, in Electrical/Computer Engineering specializing in wireless communications/DSP, system design and new product development.
  • Must be proficient in VHDL.