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Internship Asic Rtl Design Engineer Jobs in Wadsworth, OH

Innovative Technology Company focused on Essential Industry Customers

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Senior ASIC Design Engineer, BSEE required, Power Voltage Stepping App

Parma, OH · Remote

$125K - $165K/yr

You will serve as the solo ASIC Design Engineer owning architecture, transistor‐level design, simulation, verification, and delivery of custom ASICs focused on power/voltage conversion ...

Innovative Technology Company focused on Essential Industry Customers

Be Seen First

Senior PCB Design & Layout Engineer, Power-Voltage-Stepping Apps

Parma, OH · Remote

$120K - $160K/yr

Senior PCB Design & Layout Engineer - Power Management & High‐Voltage Systems Bleeding Edge Ohio ... Partner with ASIC, firmware, and mechanical engineers to integrate custom blocks and ensure system ...

Parsons

Roadway Engineering Co-Op - Fall 2026

Akron, OH · On-site

$22.93 - $40.14/hr

May be assigned to a project or organizational team, or as a design engineer for intermediate to ... Prior internship experience Security Clearance Requirement: None This position is part of our ...

Phase2 Technology

FPGA Developer

Bath, OH · On-site

$99 - $225/hr

... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...

Alpha Technologies

Mechanical Engineer I

Hudson, OH

S. in Mechanical Engineering or a related field. * 0-2 years of mechanical design experience, internships or co-ops preferred. Required skills: * Basic proficiency in 3D CAD modeling of mechanical ...

System One

Data Engineer - Contractor

Strongsville, OH · On-site

$105K - $126K/yr

Experience through internships, rotations, or early-career development programs in enterprise ... design patterns. Experience with Microsoft 365 Copilot, Copilot Studio, or AI-powered productivity ...

System One

Data Engineer - Contractor

Strongsville, OH · On-site

$105K - $126K/yr

Experience through internships, rotations, or early-career development programs in enterprise ... design patterns. Experience with Microsoft 365 Copilot, Copilot Studio, or AI-powered productivity ...

System One

Data Engineer - Contractor

Strongsville, OH · On-site

$105K - $126K/yr

Experience through internships, rotations, or early-career development programs in enterprise ... design patterns. Experience with Microsoft 365 Copilot, Copilot Studio, or AI-powered productivity ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Wadsworth, OH

Internship Asic Rtl Design Engineer information

See Wadsworth, OH salary details

$89.5K

$143.1K

$192.4K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 28, 2026, the average yearly pay for internship asic rtl design engineer in Wadsworth, OH is $143,056.00, according to ZipRecruiter salary data. Most workers in this role earn between $125,200.00 and $171,400.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you

Senior ASIC Design Engineer, BSEE required, Power Voltage Stepping App

Parma, OH • Remote

Innovative Technology Company focused on Essential Industry Customers
See more jobs at Innovative Technology Company focused on Essential Industry Customersexternal

$125K - $165K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 6 days ago

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Job description

Bleeding Edge Ohio Based Technology Firm, Newly Created Role, Tremendous Growth Opportunity: You will serve as the solo ASIC Design Engineer owning architecture, transistor‐level design, simulation, verification, and delivery of custom ASICs focused on power/voltage conversion, battery‐powered systems, and pure analog circuitry. This role also requires meaningful experience with solid‐state fabrication, semiconductor process flows, and device‐level considerations that directly influence analog/power IC performance.

Core Responsibilities

  • Analog & Power ASIC Design: Own full transistor-level lifecycle (architecture to tape-out) with required expertise in pure analog design. Design power conversion circuits—including buck/boost converters, charge pumps, battery management ICs, low/high-voltage stages, and switching/linear regulators.
  • IP Development: Develop analog/power IP blocks (biasing networks, references, amplifiers, drivers, protection circuits). Run SPICE, corner, Monte Carlo, aging, and reliability simulations.
  • Layout & Fab Interaction: Drive floorplanning, parasitic extraction, matching, and PDK usage. Integrate device physics, doping profiles, oxide variations, high-voltage structures, thermal behavior, and isolation (trench, SOI, guard rings). Evaluate process variation impacts on analog stability and noise.
  • Project Ownership: Act as the sole ASIC engineer leading technical strategy, cross-functional integration (PCB, packaging, test), and documentation.

Required Experience & Skills

  • Education & Experience: BS/MS in EE, CE, or Physics; 8+ years in transistor-level ASIC/Analog IC design as a sole project lead.
  • Pure Analog Expertise: deep experience in pure analog design—transistor-level design, compensation, stability, noise, and biasing—alongside power-conversion and battery-powered architectures.
  • Tools: Hands-on proficiency with Cadence (Virtuoso, Spectre, ADE).
  • Semiconductor Physics & Fab: Deep understanding of CMOS/BiCMOS flows, device physics, high-voltage structures, fabrication constraints (implantation, oxidation, lithography), and reliability (BTI, HCI, TDDB).

Preferred Qualifications

  • Silicon debug, bench validation, and lab bring-up experience.
  • Background in wearables, IoT, battery-powered embedded systems, or wide-bandgap devices (GaN, SiC).
  • Familiarity with mixed-signal verification methodologies.
  • BS or MS Degree in Electrical Engineering, Computer Engineering, Physics or a related area.

Very Competitive Compensation and Benefits, Call or Apply Today!

Note: we can consider on-site (relocation assistance is offered), hybrid or remote employees who can travel to HQ as needed.

Company Description

Recession Resistant Business Model, Our Systems Stabilize and Support Highly Available Applications. Using profits to build and design best of breed solutions for our customers in Essential and Other Industries. Collaborative-Team focused environment, History of Hiring very smart people with solid engineering skills, experience and education. Tech-Minded-Curious People, Terrific Culture, Competitive Salaries, Benefits, Equity