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Internship Asic Rtl Design Engineer Jobs in Ohio

Distro

Hardware Engineer

Cincinnati, OH

$120K - $160K/yr

ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...

Distro

Hardware Engineer

Cincinnati, OH

$120K - $160K/yr

ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...

SERMA Group

Productivity Engineering, part of the SERMA Group, is a leading engineering company specializing in ... The COO will be responsible for overseeing all operational activities across ASIC design execution ...

EndoSec LLC

FPGA Engineer

Cincinnati, OH

$124K - $160K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Astra North Infoteck Inc.

$92K - $107K/yr

Design, develop, and maintain responsive and scalable web applications using ReactJS. * Build ... Write and maintain unit and integration tests using React Testing Library (RTL). * Implement state ...

Apex Tool Group

Engineering Intern

Dayton, OH · On-site

$16.25 - $21.25/hr

This internship offers hands-on experience in product design, engineering documentation, and cross-functional collaboration within a manufacturing environment. The Build (Responsibilities) * Product ...

Apex Tool Group, LLC

Engineering Intern

Dayton, OH · On-site

$14.75 - $19.25/hr

This internship offers hands-on experience in product design, engineering documentation, and cross-functional collaboration within a manufacturing environment. The Build (Responsibilities) * Product ...

Woolpert

Bridge Engineer (PE)

Cincinnati, OH · On-site

$87K - $108K/yr

As a bridge engineer, you will be involved in diverse transportation projects spanning multiple ... and interns to complete bridge and other transportation tasks. * Lead and perform design for ...

Parsons

Roadway Engineering Co-Op - Fall 2026

Akron, OH · On-site

$22.93 - $40.14/hr

May be assigned to a project or organizational team, or as a design engineer for intermediate to ... Prior internship experience Security Clearance Requirement: None This position is part of our ...

Amarx Search, Inc.

Senior FPGA Engineer

Cincinnati, OH · On-site

$106K - $197K/yr

ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...

Parsons

Bridge Engineering Co-Op - Fall 2026

Akron, OH · On-site

$22.93 - $40.14/hr

May be assigned to a project or organizational team, or as a design engineer for intermediate to ... Prior internship experience Security Clearance Requirement: None This position is part of our ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Ohio

Internship Asic Rtl Design Engineer information

What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an Internship ASIC RTL Design Engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Hardware Engineer

Hardware Engineer

Distro

Cincinnati, OH

$120K - $160K/yr

Full-time

Re-posted 2 days ago

Job description

We are looking for highly talented, motivated, and versatile engineers that can create the next generation. As a Hardware Engineer at our company, you will be responsible for architecture, design, and development of next generation Electronic Safe and Arm Devices utilizing the latest state of the art technologies. ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A interfaces, communication protocols, state machines, timer chains, etc. used in Electronic Safe and Arm Devices (Fuzes) for DOD weapon systems. Microsemi / Actel is our targeted FPGA and QuestaSim is our simulation tool. The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and C# based microcontroller development. The ideal candidate for this role would share our passion for creating and innovating new technologies in a highly dynamic, fast-paced environment. Essential Functions:
Analysis of the requirements, architecture definition, design and debug of FPGA and associated hardware and microcontroller products and associated firmware. Developing Verilog HDL targeting Antifuse and enhanced Flash FPGA's. Performing effective analysis of functional issues or performance profiling with the hardware and firmware in test environments or target host systems. Contribute to process improvements to ensure hardware-firmware quality and time-to-market. Qualifications:
Bachelor's Degree and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience. Knowledge using Verilog for Logic Design. Programming experience in C for embedded systems, including development of algorithms, manipulation of data structures, and implementing highly optimized code. Experience with lab tools: Logic Analyzers, oscilloscopes, JTAG/ICE debuggers, and protocol analyzers. Familiar with hardware, software, and firmware development methodologies to ensure quality and time-to-market (design verification, code reviews, unit testing, prototyping, and product testing). Familiar working with code version control repository tools, such as Subversion (SVN), GIT or TFS. Digital Design practices and principles, logic design and architecture and experience with HDL's (i.e., Verilog, VHDL). Preferred Additional Skills:
Knowledge using SystemVerilog for verification with AVM, VMM, OVM, or UVM a plus. Developing C# source code targeting enhanced Flash Microcontrollers. Good English knowledge (speech and writing). Be action-oriented and organized. Ability to handle short notice needs/requests.
 
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