RTL Design Manager
San Jose, CA · Hybrid
As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge ... UNAVAILABLEEmployment Type: FULL_TIME
San Jose, CA · Hybrid
As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge ... UNAVAILABLEEmployment Type: FULL_TIME
San Jose, CA · Hybrid
As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge ... UNAVAILABLEEmployment Type: FULL_TIME
San Jose, CA · Hybrid
KEY RESPONSIBILITIES: * Perform RTL design of digital components. * Work with functional ... UNAVAILABLEEmployment Type: FULL_TIME
San Jose, CA · Hybrid
KEY RESPONSIBILITIES: * Perform RTL design of digital components. * Work with functional ... UNAVAILABLEEmployment Type: FULL_TIME
Benefits Full-time (Regular) 401(k) 401(k) matching Dental insurance Health insurance Life ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Benefits Full-time (Regular) 401(k) 401(k) matching Dental insurance Health insurance Life ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Richardson, TX · On-site
$177K - $348K/yr
Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Richardson, TX · On-site
$177K - $348K/yr
Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Austin, TX · On-site
Benefits Full-time (Regular) 401(k) 401(k) matching Dental insurance Health insurance Life ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Austin, TX · On-site
Benefits Full-time (Regular) 401(k) 401(k) matching Dental insurance Health insurance Life ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Folsom, CA · On-site
$177K - $348K/yr
Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Folsom, CA · On-site
$177K - $348K/yr
Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Benefits Full-time (Regular) • 401(k) • 401(k) matching • Dental insurance • Health ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Benefits Full-time (Regular) • 401(k) • 401(k) matching • Dental insurance • Health ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Benefits Full-time (Regular) • 401(k) • 401(k) matching • Dental insurance • Health ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
Benefits Full-time (Regular) • 401(k) • 401(k) matching • Dental insurance • Health ... Experienced in RTL design using VHDL/ Verilog/ System Verilog. * Strong Basics of Digital design.
San Jose, CA · On-site
$117K - $160K/yr
RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing ... UNAVAILABLEEmployment Type: FULL_TIME
San Jose, CA · On-site
$117K - $160K/yr
RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing ... UNAVAILABLEEmployment Type: FULL_TIME
Richardson, TX · On-site
$146K - $297K/yr
Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ... full-time position is: $146,000.00 - $297,000.00 a year Additional compensation may include ...
Richardson, TX · On-site
$146K - $297K/yr
Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ... full-time position is: $146,000.00 - $297,000.00 a year Additional compensation may include ...
Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer , where you ... UNAVAILABLEEmployment Type: FULL_TIME
Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer , where you ... UNAVAILABLEEmployment Type: FULL_TIME
Folsom, CA · On-site
$121K - $247K/yr
Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Folsom, CA · On-site
$121K - $247K/yr
Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Folsom, CA · On-site
$121K - $247K/yr
Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
Folsom, CA · On-site
$121K - $247K/yr
Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...
San Jose, CA · On-site
$203K - $315K/yr
San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2518 We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ...
San Jose, CA · On-site
$203K - $315K/yr
San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2518 We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ...
San Jose, CA · On-site
$203K - $315K/yr
San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2518 We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ...
Quick apply
San Jose, CA · On-site
$203K - $315K/yr
San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2518 We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ...
San Jose, CA · On-site
$203K - $315K/yr
San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2518 We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ...
San Jose, CA · On-site
$203K - $315K/yr
San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2518 We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ...
This full-time position will allow the candidate to contribute to the architecture, design of next ... RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer ...
This full-time position will allow the candidate to contribute to the architecture, design of next ... RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer ...
$146K - $297K/yr
Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ... full-time position is: $146,000.00 - $297,000.00 a year Additional compensation may include ...
$146K - $297K/yr
Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ... full-time position is: $146,000.00 - $297,000.00 a year Additional compensation may include ...
Must be in San Diego full time, 5 days a week Ideal candidate will have: * 6-10+ years of work experience with RTL/FPGA design (Verilog, System verilog), embedded system architecture and Verification
Must be in San Diego full time, 5 days a week Ideal candidate will have: * 6-10+ years of work experience with RTL/FPGA design (Verilog, System verilog), embedded system architecture and Verification
Sunnyvale, CA · On-site
$159K - $194K/yr
Fulltime Experience: 10-15 Years About the role: Design Verification engineer for wearables silicon accelerator IPs -- testbench development, coverage-driven verification, RTL debug, and power ...
Quick apply
Sunnyvale, CA · On-site
$159K - $194K/yr
Fulltime Experience: 10-15 Years About the role: Design Verification engineer for wearables silicon accelerator IPs -- testbench development, coverage-driven verification, RTL debug, and power ...
$80.5K - $89.8K
0% of jobs
$89.8K - $99K
0% of jobs
$99K - $108.3K
1% of jobs
$108.3K - $117.6K
0% of jobs
$117.6K - $126.9K
0% of jobs
$130.7K is the 25th percentile. Wages below this are outliers.
$126.9K - $136.1K
57% of jobs
$140.1K is the 75th percentile. Wages above this are outliers.
$136.1K - $145.4K
38% of jobs
$145.4K - $154.7K
0% of jobs
$154.7K - $164K
1% of jobs
$164K - $173.2K
1% of jobs
$173.2K - $182.5K
1% of jobs
$80.5K
$139.4K
$182.5K
| Aspect | Full Time Rtl Design | Full Time Digital IC Design |
|---|---|---|
| Credentials | Bachelor's in Electrical Engineering or Computer Engineering | Bachelor's or higher in Electrical Engineering or related field |
| Work Environment | Design teams, semiconductor companies, EDA tool usage | Integrated circuit design teams, semiconductor industry, EDA tools |
| Industry Usage | Primarily in digital hardware development |
Full Time Rtl Design focuses on creating register transfer level code for digital circuits, often as part of a larger IC design process. Full Time Digital IC Design encompasses a broader scope, including RTL design, logic synthesis, and physical implementation. While RTL Design is a key component, Digital IC Design involves additional stages of the chip development process.
The most popular types of Rtl Design jobs are:
States with the most job openings for Full Time Rtl Design jobs include:
The top searched job categories for Full Time Rtl Design jobs are:

8.6
Based on 13 frontline employees who took The Breakroom Quiz
27th of 159 rated electronics manufacturers
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge designs.As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
LOCATION:
San Jose, CA
This role is not eligible for visa sponsorship.
#LI-SL2
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMEGet the full story on Breakroom
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Computer and electronic product manufacturing and manufacturing
5,001 - 10,000 Employees
Sunnyvale, CA, US