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Part Time Rtl Design Jobs (NOW HIRING)

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

This is a fully remote, part-time engagement requiring approximately 20-40 hours per week , depending on your availability. Requirements Key Responsibilities * Design realistic chip architecture, RTL ...

Booz Allen Hamilton, Inc.

FPGA Developer

Beavercreek, OH · On-site

$99K - $225K/yr

Experience using Vivado for embedded system design * Experience with Digital Signal Processing ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...

All Jobspart time JobsPart Time Rtl Design Jobs

Part Time Rtl Design information

See salary details

$80.5K

$139.4K

$182.5K

How much do part time rtl design jobs pay per year?

As of Aug 22, 2026, the average yearly pay for part time rtl design in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a part time RTL design job?

Part Time RTL (Register Transfer Level) Design jobs involve creating and verifying digital circuit designs, typically using hardware description languages like Verilog or VHDL, but on a part-time basis. These roles are common in the semiconductor and electronics industries, where engineers are responsible for developing the logic that controls how data is processed within chips. Part-time RTL designers may work on specific modules, collaborate with verification teams, and help optimize designs for performance and efficiency. This arrangement offers flexibility while still requiring strong technical and problem-solving skills.

What skills and qualifications are needed for a part time RTL design engineer?

To excel as a Part Time RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, often supported by a degree in electrical or computer engineering. Familiarity with FPGA/ASIC design tools like Synopsys, Cadence, or Xilinx, and experience with simulation and verification environments are typically required. Strong problem-solving ability, attention to detail, and effective communication skills help you collaborate with teams and troubleshoot complex design issues. These skills ensure accurate hardware implementation, efficient project execution, and successful delivery of reliable digital systems.

What are common challenges faced by part time RTL design engineers, and how can they be addressed?

Part-time RTL Design engineers often face the challenge of staying updated with ongoing project changes and maintaining effective communication with full-time team members. Since RTL design work typically involves close collaboration with verification, synthesis, and physical design teams, it’s important for part-time engineers to use collaborative tools and attend key meetings, even if asynchronously. Well-organized documentation and clear task tracking can help bridge any gaps caused by reduced hours. Regular check-ins and proactive communication are essential to ensure alignment with project goals and timelines.

What is the difference between Part Time Rtl Design vs Part Time Digital IC Design?

AspectPart Time Rtl DesignPart Time Digital IC Design
Required SkillsVerilog/VHDL, RTL coding, FPGA/ASIC designRTL coding, digital circuit design, verification
Work EnvironmentDesign teams, semiconductor companies, consulting firmsSemiconductor industry, chip design companies
CertificationsNone specific, but FPGA/ASIC experience preferredSimilar, often requiring RTL design experience
Job FocusRTL coding and verification for digital circuitsDesign and verification of digital integrated circuits

Part Time Rtl Design and Part Time Digital IC Design roles both involve RTL coding and digital circuit design, often within semiconductor companies. The main difference lies in scope: RTL Design focuses on coding and verification at the RTL level, while Digital IC Design encompasses the entire chip design process. Both roles require similar skills and certifications, making them closely related in the industry.

Is part time RTL design a good career?

Part time RTL (Register Transfer Level) design can be a viable career option for those with skills in digital logic, hardware description languages like VHDL or Verilog, and familiarity with FPGA or ASIC development. It offers flexibility and opportunities in semiconductor and electronics industries, but may have limited full-time growth compared to full-time roles. Success depends on skill level, industry demand, and the ability to work independently or as part of a team.

What is the future of part time RTL design?

Part-time RTL design roles are expected to remain in demand as companies seek flexible engineering talent for hardware and chip development. Skills in hardware description languages like VHDL or Verilog and familiarity with FPGA or ASIC design tools will continue to be valuable in this evolving field.
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Part Time Rtl Design jobs near you
Infographic showing various Part Time Rtl Design job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

ASIC/SoC Design & Verification Engineer

Weekday AI

Remote

$70 - $100/hr

Part-time

Posted 24 days ago

Job description

This role is for one of our clients
Compensation: $70-$100 per hour
Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.
Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.
This is a fully remote, part-time engagement requiring approximately 20-40 hours per week, depending on your availability.
Requirements
Key Responsibilities
  • Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
  • Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
  • Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
  • Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
  • Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
  • Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.
Required Qualifications
  • Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
  • Strong proficiency in SystemVerilog and Verilog.
  • Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
  • Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
  • Deep expertise in one or more of the following areas:
    • RTL Design and Microarchitecture
    • Functional Verification (UVM, SVA, Cocotb, testbench development)
    • IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
    • Formal Verification and Coverage Closure
    • Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
    • Analog/Mixed-Signal Design Verification
    • Hardware Specification Development and Technical Documentation
  • Ability to commit 20-40 hours per week with reliable weekday availability.
  • Strong written communication skills and the ability to work independently in a remote environment.
Preferred Qualifications
  • Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
  • Graduate research or industry experience in semiconductor design, verification, or computer architecture.
  • Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
  • Experience mentoring engineers or reviewing complex technical designs.
Why Join
  • Help shape how advanced AI systems understand and solve real-world semiconductor engineering challenges.
  • Apply your practical chip design and verification expertise to improve the next generation of AI models.
  • Work alongside experienced hardware engineers, researchers, and AI specialists on high-impact projects.
  • Enjoy the flexibility of a fully remote engagement with opportunities for continued collaboration based on performance.
Equal Opportunity
We are committed to creating an inclusive environment and welcome applications from qualified professionals of all backgrounds. Reasonable accommodations are available throughout the application and engagement process.
Contract & Engagement Details
  • Independent contractor engagement.
  • Fully remote with flexible working hours.
  • Expected commitment of approximately 20-40 hours per week.
  • Project duration may be extended, shortened, or concluded based on project requirements and individual performance.
  • Work does not require access to confidential or proprietary information from any current or former employer.
  • Payments are issued weekly based on approved work completed.
  • At this time, we are unable to support H1-B or STEM OPT candidates.

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