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Full Time Rtl Design Jobs (NOW HIRING)

Siri InfoSolutions Inc

Design Engineer III

Sunnyvale, CA · On-site

$159K - $194K/yr

Fulltime Experience: 10-15 Years About the role: Design Verification engineer for wearables silicon accelerator IPs -- testbench development, coverage-driven verification, RTL debug, and power ...

Micron

Intern - HBM SoC RTL Design Engineer

Folsom, CA · On-site

$38.84 - $50.24/hr

Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ... The US base salary range that Micron Technology estimates it could pay for this full-time position ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... The US salary range for this full-time position is $127,400 to $236,600

Mirafra Technology

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong ... RTL design experience and/or very strong OOPs programming experience is also a plus. Good written ...

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

Exempt / Full-time Salary Range: $145k - $175k Annually DoD Secret clearance (or higher) REQUIRED ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

AERONIX INC

Senior FPGA Design Engineer

Melbourne, FL · On-site

$145K - $175K/yr

Exempt / Full-time Salary Range: $145k - $175k Annually DoD Secret clearance (or higher) REQUIRED ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... The US salary range for this full-time position is $127,400 to $287,600. Our salary ranges are ...

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Full Time Rtl Design information

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$80.5K

$139.4K

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How much do full time rtl design jobs pay per year?

As of Sep 8, 2026, the average yearly pay for full time rtl design in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Full Time Rtl Design vs Full Time Digital IC Design?

AspectFull Time Rtl DesignFull Time Digital IC Design
CredentialsBachelor's in Electrical Engineering or Computer EngineeringBachelor's or higher in Electrical Engineering or related field
Work EnvironmentDesign teams, semiconductor companies, EDA tool usageIntegrated circuit design teams, semiconductor industry, EDA tools
Industry UsagePrimarily in digital hardware development

Full Time Rtl Design focuses on creating register transfer level code for digital circuits, often as part of a larger IC design process. Full Time Digital IC Design encompasses a broader scope, including RTL design, logic synthesis, and physical implementation. While RTL Design is a key component, Digital IC Design involves additional stages of the chip development process.

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States with the most job openings for Full Time Rtl Design jobs include:

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Full Time Rtl Design jobs near you
Infographic showing various Full Time Rtl Design job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

Design Engineer III

Sunnyvale, CA • On-site

Siri InfoSolutions Inc
IT Services • 201 - 500 employees
Learn more about Siri InfoSolutions Incexternal

$159K - $194K/yr

Full-time

Posted 25 days ago

Job description

Position: Design Engineer III
Location: Sunnyvale, CA- Onsite

Duration: Fulltime

Experience: 10-15 Years

Job Description

About the role: Design Verification engineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.

 

Responsibilities:
Develop and execute verification plans for RTL blocks/IPs across the subsystem.
Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Drive functional coverage and assertion (SVA) closure; run and triage regressions.
Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
Build power/perf dashboard for tracking and publishing Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
Contribute to automation of verification/regression and power/performance measurement flows (Python).

 

Minimum Qualifications:
Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
Working knowledge of RTL design principles and digital design fundamentals.
Proficiency in Python (or Perl) scripting for automation.

 

Preferred Qualifications:
Experience with power measurement tools — PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).
Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
Formal verification and/or emulation (Palladium / Zebu) experience.
Familiarity with the RTL-to-GDSII flow.
Data analysis / ML approaches for coverage or debug triage.
Previous Meta experience preferred.

Education: BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).

Top 3 Must-Have Skills:
SystemVerilog / UVM testbench development.
Functional coverage + assertion-based verification and coverage closure.
RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.

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About Siri Infosolutions

Sourced by ZipRecruiter

Our team of experts first gather each and every requirement of yours. Our research and development team then sit around those requirements and come up with a plan. Our implementation team then executes that plan for optimal results. After that our support team remains in constant touch with you during and after the entire process.

Industry

It services

Company size

201 - 500 Employees

Headquarters location

Edison, NJ, US

Year founded

2005

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