Methodology Engineer - Static RTL Verification
$159K - $195K/yr
Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ... UNAVAILABLEEmployment Type: FULL_TIME
$159K - $195K/yr
Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ... UNAVAILABLEEmployment Type: FULL_TIME
$159K - $195K/yr
Design and execute toolqualification regressions across complex AMD SoC designs, ensuring ... UNAVAILABLEEmployment Type: FULL_TIME
$144K - $176K/yr
Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong ... RTL design experience and/or very strong OOPs programming experience is also a plus. Good written ...
$144K - $176K/yr
Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong ... RTL design experience and/or very strong OOPs programming experience is also a plus. Good written ...
Sunnyvale, CA · On-site
$159K - $194K/yr
Sunnyvale, CA / Redmond, WA / Austin, TX Work Type: Full-Time, Onsite (Hybrid - No Remote Allowed ... Debug simulation failures, analyze root causes, and work closely with RTL design teams. * Execute ...
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Sunnyvale, CA · On-site
$159K - $194K/yr
Sunnyvale, CA / Redmond, WA / Austin, TX Work Type: Full-Time, Onsite (Hybrid - No Remote Allowed ... Debug simulation failures, analyze root causes, and work closely with RTL design teams. * Execute ...
San Jose, CA · On-site
$220K - $296K/yr
San Jose, CA ( This position requires a full-time, on-site presence in our San Jose, CA office ... Develop RTL design for custom logic around the interfaces, including protocol adaptation and data ...
Quick apply
San Jose, CA · On-site
$220K - $296K/yr
San Jose, CA ( This position requires a full-time, on-site presence in our San Jose, CA office ... Develop RTL design for custom logic around the interfaces, including protocol adaptation and data ...
Greenville, SC · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
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Greenville, SC · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Melbourne, FL · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
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Melbourne, FL · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Melbourne, FL · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Quick apply
Melbourne, FL · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Greenville, SC · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Quick apply
Greenville, SC · On-site
$120K - $150K/yr
Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
San Jose, CA · On-site
$220K - $296K/yr
San Jose, CA ( This position requires a full-time, on-site presence in our San Jose, CA office ... Develop RTL design for custom logic around the interfaces, including protocol adaptation and data ...
San Jose, CA · On-site
$220K - $296K/yr
San Jose, CA ( This position requires a full-time, on-site presence in our San Jose, CA office ... Develop RTL design for custom logic around the interfaces, including protocol adaptation and data ...
San Jose, CA · Hybrid
You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in ... UNAVAILABLEEmployment Type: FULL_TIME
San Jose, CA · Hybrid
You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in ... UNAVAILABLEEmployment Type: FULL_TIME
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
San Jose, CA · On-site
$220K - $296K/yr
San Jose, CA ( This position requires a full-time, on-site presence in our San Jose, CA office ... Develop RTL design for custom logic around the interfaces, including protocol adaptation and data ...
San Jose, CA · On-site
$220K - $296K/yr
San Jose, CA ( This position requires a full-time, on-site presence in our San Jose, CA office ... Develop RTL design for custom logic around the interfaces, including protocol adaptation and data ...
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Milpitas, CA · On-site
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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Milpitas, CA · On-site
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
San Diego, CA · On-site
$108K - $143K/yr
Candidates should possess a strong educational background in Electrical Engineering or Computer Science and extensive experience in RTL design and IP development. This full-time role offers a ...
San Diego, CA · On-site
$108K - $143K/yr
Candidates should possess a strong educational background in Electrical Engineering or Computer Science and extensive experience in RTL design and IP development. This full-time role offers a ...
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Quick apply
Saratoga, CA · On-site
$150K - $220K/yr
This role sits at the intersection of RTL design and functional verification, requiring a strong ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Ptpx, Power Artist, etc.) * Strong experience in RTL design, simulation, and synthesis ... UNAVAILABLEEmployment Type: FULL_TIME
Ptpx, Power Artist, etc.) * Strong experience in RTL design, simulation, and synthesis ... UNAVAILABLEEmployment Type: FULL_TIME
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... Work with physical design team on the timing closure of the cache subsystem. 3+ years of full time ...
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... Work with physical design team on the timing closure of the cache subsystem. 3+ years of full time ...
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... years of full time ASIC design experiencememory system developmentRTL/micro-architecture ...
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... years of full time ASIC design experiencememory system developmentRTL/micro-architecture ...
THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ... UNAVAILABLEEmployment Type: FULL_TIME
THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ... UNAVAILABLEEmployment Type: FULL_TIME
$80.5K - $89.8K
0% of jobs
$89.8K - $99K
0% of jobs
$99K - $108.3K
1% of jobs
$108.3K - $117.6K
0% of jobs
$117.6K - $126.9K
0% of jobs
$130.7K is the 25th percentile. Wages below this are outliers.
$126.9K - $136.1K
57% of jobs
$140.1K is the 75th percentile. Wages above this are outliers.
$136.1K - $145.4K
38% of jobs
$145.4K - $154.7K
0% of jobs
$154.7K - $164K
1% of jobs
$164K - $173.2K
1% of jobs
$173.2K - $182.5K
1% of jobs
$80.5K
$139.4K
$182.5K
| Aspect | Full Time Rtl Design | Full Time Digital IC Design |
|---|---|---|
| Credentials | Bachelor's in Electrical Engineering or Computer Engineering | Bachelor's or higher in Electrical Engineering or related field |
| Work Environment | Design teams, semiconductor companies, EDA tool usage | Integrated circuit design teams, semiconductor industry, EDA tools |
| Industry Usage | Primarily in digital hardware development |
Full Time Rtl Design focuses on creating register transfer level code for digital circuits, often as part of a larger IC design process. Full Time Digital IC Design encompasses a broader scope, including RTL design, logic synthesis, and physical implementation. While RTL Design is a key component, Digital IC Design involves additional stages of the chip development process.

$159K - $195K/yr
Full-time
Posted 12 days ago
8.4
Based on 7 frontline employees who took The Breakroom Quiz
22nd of 139 rated electronics manufacturers
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
This role involves planning, developing, and maintaining AMD EDA tools focused on RTL static checks and supporting frameworks. These tools are used across AMD SoC teams to help ensure highquality RTL design.
THE PERSON
You are motivated by solving complex engineering problems and enjoy working with digital design, SystemVerilog, and static RTL checking methodologies. You collaborate effectively with engineers across teams and geographies and are comfortable communicating technical concepts with diverse partners. You approach problems analytically, take ownership of your work, and continuously build new skills.
KEY RESPONSIBILITIES
PREFERRED EXPERIENCE
ACADEMIC CREDENTIALS
This role is not eligible for visa sponsorship.
#LI-DP1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMESourced by ZipRecruiter
Computer and electronic product manufacturing and manufacturing
5,001 - 10,000 Employees
Sunnyvale, CA, US