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Full Time Rtl Design Jobs (NOW HIRING)

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... The US salary range for this full-time position is $127,400 to $236,600. Our salary ranges are ...

SoC Design and Verification

Hillsboro, OR · On-site

$148K - $180K/yr

At least 7 years of experience in RTL Design verification of SoCs (VHDL, Verilog, System Verilog ... Note:- * This is a Full-Time & Permanent job opportunity for you. * Only US Citizen , Green Card ...

Deep expertise in SystemVerilog for RTL design, microarchitecture, and integration * Strong ... DSLs for RTL generation The expected base salary range for this full-time position across US ...

Showing results 41-60

Full Time Rtl Design information

See salary details

$80.5K

$139.4K

$182.5K

How much do full time rtl design jobs pay per year?

As of Aug 19, 2026, the average yearly pay for full time rtl design in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Full Time Rtl Design vs Full Time Digital IC Design?

AspectFull Time Rtl DesignFull Time Digital IC Design
CredentialsBachelor's in Electrical Engineering or Computer EngineeringBachelor's or higher in Electrical Engineering or related field
Work EnvironmentDesign teams, semiconductor companies, EDA tool usageIntegrated circuit design teams, semiconductor industry, EDA tools
Industry UsagePrimarily in digital hardware development

Full Time Rtl Design focuses on creating register transfer level code for digital circuits, often as part of a larger IC design process. Full Time Digital IC Design encompasses a broader scope, including RTL design, logic synthesis, and physical implementation. While RTL Design is a key component, Digital IC Design involves additional stages of the chip development process.

More about Full Time Rtl Design jobs

What are the most commonly searched types of Rtl Design jobs?

The most popular types of Rtl Design jobs are:

What states have the most Full Time Rtl Design jobs?

States with the most job openings for Full Time Rtl Design jobs include:

Infographic showing various Full Time Rtl Design job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

Principal Logic Design Engineer

Rambus

Hillsboro, OR • Hybrid

$127K - $236K/yr

Full-time

Medical, Dental, Retirement

Re-posted 24 days ago


Job description

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hillsboro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. 

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next- generation high performance and cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you. 

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. 


  • Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces 
  • Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data 
  • Collaborate closely with verification team to shape test plans and improve verification coverage 
  • Work with physical design team to understand and resolve timing, power, and congestion challenges 
  • Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary 
  • Provide technical support to FAE team on pre-sales customer engagements 
  • Provide technical support to AE team on post-sales customer deliveries 

  • Strong System Verilog/Verilog RTL design expertise 
  • Questa/Incisive/VCS simulator experience 
  • Python/Perl/TCL scripting experience 
  • Ability to learn quickly and work independently 
  • Solid communication and project management skills 
  • 10+ years of logic design experience (ASIC/FPGA) with BSEE, or  
  • 8+ years of logic design experience (ASIC/FPGA) with MSEE 

Definite Plus: 

  • ASIC synthesis, timing constraint, CDC/RDC experience 
  • UVM Verification experience 
  • Memory (HBM, LPDDR) expertise 
  • AMBA AXI or CHI design experience 

About Rambus 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.  

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.  

The US salary range for this full-time position is $127,400 to $236,600. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be