$140K - $150K/yr
DFT Verification (including post place-and-route timing simulations). * Work with Product Engineering team to bring up scan & mbist patterns on ATE. * Support silicon production activities including ...
$140K - $150K/yr
DFT Verification (including post place-and-route timing simulations). * Work with Product Engineering team to bring up scan & mbist patterns on ATE. * Support silicon production activities including ...
$140K - $150K/yr
DFT Verification (including post place-and-route timing simulations). * Work with Product Engineering team to bring up scan & mbist patterns on ATE. * Support silicon production activities including ...
Austin, TX · On-site
We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips ...
Austin, TX · On-site
We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips ...
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
Irvine, CA · On-site
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...
Quick apply
Irvine, CA · On-site
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA - Open for Onsite/Remote (Should be in PST timings though) Visa- USC/GC Experience : 10+ years of hands-on experience in ASIC Design-for-Test ...
Quick apply
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA - Open for Onsite/Remote (Should be in PST timings though) Visa- USC/GC Experience : 10+ years of hands-on experience in ASIC Design-for-Test ...
Chandler, AZ · On-site
$120 - $160/hr
R-10064841As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead ...
Chandler, AZ · On-site
$120 - $160/hr
R-10064841As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead ...
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...
Quick apply
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...
Chandler, AZ · On-site
As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product ...
Chandler, AZ · On-site
As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product ...
Santa Clara, CA · On-site
$100K - $500K/yr
You have a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with 10+ years of relevant DFT experience. * You have hands-on experience with ...
Santa Clara, CA · On-site
$100K - $500K/yr
You have a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with 10+ years of relevant DFT experience. * You have hands-on experience with ...
Austin, TX · On-site
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
Austin, TX · On-site
$106K - $184K/yr
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...
San Jose, CA · Remote
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...
Quick apply
San Jose, CA · Remote
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...
San Jose, CA · On-site
$194K/yr
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote however once/month in office. PST time zone preferred Designation: Associate Experience Required: * 10+ years of hands-on ...
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San Jose, CA · On-site
$194K/yr
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote however once/month in office. PST time zone preferred Designation: Associate Experience Required: * 10+ years of hands-on ...
Austin, TX · On-site
Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...
Austin, TX · On-site
Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...
As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product ...
As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product ...
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ...
Quick apply
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ...
OR · On-site +1
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
OR · On-site +1
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Santa Clara, CA · On-site
DEF Engineer Location: Santa Clara Skill: DFT Scan Insertion, ATPG Validation Tools: Mentor Tessent (Siemens), Synopsys DFT Compiler HC required: 1 Experience 8 to 12 years max
Santa Clara, CA · On-site
DEF Engineer Location: Santa Clara Skill: DFT Scan Insertion, ATPG Validation Tools: Mentor Tessent (Siemens), Synopsys DFT Compiler HC required: 1 Experience 8 to 12 years max
Plano, TX · Remote
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...
Quick apply
Plano, TX · Remote
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...
Austin, TX · On-site
Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...
Austin, TX · On-site
Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...
$73K - $89K
10% of jobs
$101.9K is the 25th percentile. Wages below this are outliers.
$89K - $105K
19% of jobs
$105K - $121K
17% of jobs
The median wage is $122.7K / yr.
$121K - $137K
39% of jobs
$137K - $153K
12% of jobs
$153K - $169K
1% of jobs
$169K - $185K
1% of jobs
$185K - $201K
1% of jobs
$201K - $217K
0% of jobs
$217K - $233K
0% of jobs
$233K - $249K
0% of jobs
$73K
$129.5K
$249K
| Aspect | Dft Engineer | Test Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electronics, Electrical, or related fields; certifications in DFT techniques | Bachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies |
| Work Environment | Design and implementation of DFT strategies during IC development | Testing, validation, and debugging of electronic products and systems |
| Employer & Industry Usage | Semiconductor companies, IC design firms | Consumer electronics, automotive, telecommunications industries |
While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.
Cities with the most Dft Engineer job openings:
The most popular types of Dft Engineer jobs are:
States with the most job openings for Dft Engineer jobs include:
The top searched job categories for Dft Engineer jobs are:

Job Description
Ambarella, a worldwide leader in edge AI semiconductors and software, is on a mission to bring artificial intelligence to all types of everyday devices, for enhanced environmental perception in everything from security cameras to robots to autonomous vehicles.
Position Responsibilities:
DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post-Production forcomplex multi-million gate Computer Vision SoC.
Analyze clocking scheme and implement clock control structure for at-speed scan testing
Develop/Generate high-quality scan and mbist patterns.
DFT Verification (including post place-and-route timing simulations).
Work with Product Engineering team to bring up scan & mbist patterns on ATE.
Support silicon production activities including failure diagnosis and test optimization.
Minimum Requirements:
MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5 years of experience in DFT implementation
Knowledge of DFT fundamentals
Knowledge of Logic design and timing
Knowledge of Verilog and Python
Knowledge of Mentor Tessent tools is a plus
Knowledge of scan diagnostics is a plus
The base salary range is $140,000- $150,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
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Semiconductor and electronic component manufacturing
501 - 1,000 Employees
Santa Clara, CA, US
2004