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Dft Engineer Jobs (NOW HIRING)

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...

GlobalFoundries

DFT Engineer

Austin, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Broadcom, Inc.

DFT Engineer

Austin, TX · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

NXP Semiconductors

Senior DfT Engineer

Chandler, AZ

As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be: 1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...

K2 Space

Senior DFT Engineer

OR · On-site +1

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Broadcom

DFT Engineer

Austin, TX

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology. Required Qualifications: * BSEE with 12+ years of relevant engineering experience or MSEE ...

Apple

SoC DFT Engineer

Austin, TX · On-site

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

K2 Space

Senior DFT Engineer

Seattle, WA

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...

Apple

SoC DFT Engineer

Austin, TX

$144K - $263K/yr

  • Medical

  • Dental

  • Retirement

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Apple

SoC DFT Engineer

Austin, TX

$144K - $263K/yr

  • Medical

  • Dental

  • Retirement

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Apple

SoC DFT Engineer

Austin, TX · On-site

Description As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

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Showing results 21-40

All JobsDft Engineer Jobs

Dft Engineer information

See salary details

$73K

$129.5K

$249K

How much do dft engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT engineer?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within semiconductor and integrated circuit design, focusing on ensuring chip testability and manufacturability. It offers steady demand due to the need for quality control in electronics manufacturing and typically requires knowledge of digital design, testing methodologies, and tools like EDA software. Career growth depends on industry trends, technical skills, and certifications, making it a viable option for those interested in hardware design and testing.

How much do DFT engineers make?

Design for Test (DFT) engineers typically earn between $80,000 and $130,000 annually, depending on experience, location, and industry. Senior DFT engineers with specialized skills in automation and verification can earn higher salaries, especially in high-demand tech regions.

What does a Dft engineer do?

A DFT (Design for Test) engineer designs and implements testing strategies to ensure integrated circuits and electronic systems are defect-free and function correctly. They develop test plans, create test hardware and software, and work closely with design teams to improve testability and reduce manufacturing defects. Proficiency in scripting, testing tools, and industry standards is essential for this role.

What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What is a DFT engineer?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.
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Dft Engineer jobs near you
Infographic showing various Dft Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $129,511 per year, or $62.3 per hour.

Lead ASIC DFT Engineer

Accord Technologies Inc.

San Jose, CA • On-site

Full-time

Re-posted 24 days ago

Job description

Title - Lead ASIC DFT Engineer
Location – San Jose, CA -
Open for Onsite/Remote (Should be in PST timings though)
Visa- USC/GC
Job Description
Experience : 10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

 Required Skills & Qualifications:

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

 Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.