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Dft Engineer Jobs (NOW HIRING)

DFT Engineer

Austin, TX · On-site

$108K - $192K/yr

Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...

DFT Engineer

Austin, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating ...

Staff DFT Engineer

Santa Clara, CA · On-site

$130K - $180K/yr

What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role ...

As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and implementing ...

Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating ...

A Bachelor's or Master's Degree, in Electrical or Computer Engineering required with at least 10 years of good experience of latest innovative trends in DFT, test and silicon engineering. * Good ...

Senior DFT Engineer

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

OR · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating ...

ASIC DFT Engineer

Fort Collins, CO · On-site

$108K - $172K/yr

Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating ...

As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design.- Developing and implementing DFT ...

Principal DFT Engineer

$180K - $220K/yr

Principal DFT Engineer : Developing silicon for AI Computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote ...

Principal DFT Engineer

OR · Remote

$180K - $220K/yr

Principal DFT Engineer : Developing silicon for AI Computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote ...

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design.- Developing and implementing DFT ...

Verification of DFT Logic and analysis of fault coverage * Timing analysis for DFT Modes Minimum Requirements: * MSEE in Electrical / Computer Engineering * Knowledge of DFT fundamentals * Knowledge ...

What You Can Expect We are seeking a Staff DFT Engineer with 5+ years of hands-on implementation experience across MBIST, BISR, Boundary Scan, and IJTAG . This is a highly execution-driven role ...

Description As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

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Dft Engineer information

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$73K

$129.5K

$249K

How much do dft engineer jobs pay per year?

As of Jun 5, 2026, the average yearly pay for dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT Engineer, and why are they important?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within electronic design automation focused on designing chips that are easy to test. It offers steady demand in semiconductor and electronics industries, with opportunities for growth and skill development in areas like automation tools and verification techniques. Career prospects are generally favorable for those with strong technical skills and knowledge of testing methodologies.

What are some common challenges faced by DFT Engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What are DFT Engineers?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.
More about Dft Engineer jobs
What cities are hiring for Dft Engineer jobs? Cities with the most Dft Engineer job openings:
What are the most commonly searched types of Dft Engineer jobs? The most popular types of Dft Engineer jobs are:
What states have the most Dft Engineer jobs? States with the most job openings for Dft Engineer jobs include:
Infographic showing various Dft Engineer job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 67% In-person, and 33% Hybrid job distribution, with an average salary of $129,511 per year, or $62.3 per hour.
DFT Engineer

$108K - $192K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 20 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 139 rated electronics manufacturers


Job description

Please Note:
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Job Description:
As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.
Key Responsibilities:
  • Work closely with the ATE engineer on yield improvement and analysis.
  • Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
  • Participate in block and chip-level DFT implementation, developing and executing all related tasks.
  • Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
  • Perform ATPG and pattern simulation for both MBIST and scan.
  • Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
  • Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.

Required Qualifications:
  • BSEE with 8+ years of relevant experience or MSEE with 6+ years of relevant experience.
  • Required experience in silicon bring-up and yield improvement.
  • Solid understanding of DFT techniques.
  • Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
  • Experience in MBIST architecture and insertion.
  • Experience in analyzing and debugging simulation failures.
  • Solid understanding of digital logic fundamentals.
  • Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
  • Proficiency with Perl or other scripting languages.
  • Strong communication and interpersonal skills.
  • Plus: Experience in STA constraint development in DFT modes

Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $108,000 - $192,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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