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Dft Engineer Jobs (NOW HIRING)

Broadcom, Inc.

DFT Engineer

Austin, TX · On-site

Work closely with the ATE engineer on yield improvement and analysis. * Develop ATE patterns, manage the hand-off process, and perform silicon debugging. * Participate in block and chip-level DFT ...

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the detailed for your reference - Experience 10+ years of hands-on experience in ASIC Design-for-Test ...

Apple

SoC DFT Engineer

Austin, TX · On-site

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

GlobalFoundries

DFT Engineer

Austin, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Phizenix

Staff DFT Engineer

Santa Clara, CA · On-site

What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role ...

Qualcomm

DFT Engineer

San Diego, CA · On-site

$140K - $210K/yr

Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ...

Phizenix

Staff DFT Engineer

Santa Clara, CA · On-site

$130K - $180K/yr

What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role ...

K2 Space

Senior DFT Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

New

K2 Space

OR

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Broadcom

ASIC DFT Engineer

San Jose, CA · On-site

$121K - $195K/yr

Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. * Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and ...

Siri InfoSolutions Inc

Sr. DFT Engineer (Remote)

San Jose, CA · On-site

$122K - $168K/yr

Role: Sr. DFT Engineer Location: San Jose, CA-Remote Experience: 5+ Years Seeking Candidate Exposure with ATGP and SSM / SSN (Streaming Scan Network) developed by Siemens (Tessent) which Decouples ...

Broadcom

DFT Engineer

Austin, TX

Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology. Required Qualifications: * BSEE with 12+ years of relevant engineering experience or MSEE ...

Marvell

Staff DFT Engineer

Santa Clara, CA

What You Can Expect We are seeking a Staff DFT Engineer with 5+ years of hands-on implementation experience across MBIST, BISR, Boundary Scan, and IJTAG . This is a highly execution-driven role ...

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All JobsDft Engineer Jobs

Dft Engineer information

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$73K

$129.5K

$249K

How much do dft engineer jobs pay per year?

As of Jul 4, 2026, the average yearly pay for dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT Engineer, and why are they important?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within semiconductor and integrated circuit design, focusing on ensuring manufacturability and testability of chips. It offers steady demand due to the ongoing need for quality and reliability in electronics, and requires skills in digital design, verification, and tools like EDA software. Career growth depends on industry trends and technical expertise, often involving certifications and continuous learning.

What engineers make $500,000?

Senior engineers in specialized fields such as petroleum, aerospace, or software engineering with extensive experience and advanced skills can earn $500,000 or more annually. High compensation often involves leadership roles, bonuses, stock options, or working in high-demand industries with complex projects.

How much do DFT engineers make?

Design for Test (DFT) engineers typically earn between $80,000 and $130,000 annually, depending on experience, location, and industry. Senior DFT engineers with specialized skills in automation and verification can earn higher salaries, often exceeding $150,000. Compensation may also include bonuses and benefits related to their expertise in integrated circuit testing and design validation.

What does a DFT engineer do?

A DFT (Design for Test) engineer designs and implements test strategies and methodologies to ensure integrated circuits and electronic devices are functional and defect-free. They develop test plans, create test patterns, and work with CAD tools to improve test coverage and manufacturability, often collaborating with design and manufacturing teams. Proficiency in scripting, testing tools, and industry standards is essential for this role.

What are some common challenges faced by DFT Engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What are DFT Engineers?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.
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Dft Engineer jobs near you
dft engineer - 1293079

dft engineer - 1293079

Ethan Alexander Group

Irvine, CA • On-site

Full-time

Posted 13 days ago

Job description

DFT Engineer


Responsibilities

  • Define & document DFT requirements/Specifications for IP/Block and Chip level
  • Execute DFT Lint to identify scan DRC violations and resolution
  • Top level and hard macro block level scan insertion with high EDT compression ratio (Hybrid LBIST, EDT IP/ATPG, LPCT EDT, AC scan verification with high speed PLL, MBIST, and IJTAG)
  • Plan and Insert MBIST and memory repair (BISR) at RTL
  • Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests
  • ATPG pattern verification on pre/post-route gate-level netlist including 0-delay and SDF
  • Work with backend team for the MBIST/Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closure
  • Support test engineer for pattern generation, tester debug and failure analysis.
  • Work with Test Engineering team during Silicon bring-up and creating flow/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), MBIST patterns on ATE for development and production programs
  • Expert knowledge of Mentor Tessent toolchain

Job Requirements

  • Hands-on hierarchical DFT flow experience from RTL to netlist
  • Strong knowledge and experience with both JTAG (IEEE1149.1) and IJTAG (1687)
  • Experience in inserting EDT, wrapper cells and OCC
  • Experience in analyzing DFT DRC violations and fault coverage analysis
  • Expertise in ATPG. Debug and resolve ATPG DRC and chain trace issues
  • Gate level simulations and debug; both 0-delay and with SDF DFT
  • Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation
  • Experience in debugging tester/ATE failures, silicon bring-up and yield and test time improvement
  • Experience in Perl/TCL scripting and good verbal/written communication skills
  • 7+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success