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Dft Engineer Jobs (NOW HIRING)

Broadcom, Inc.

ASIC DFT Engineer

Fort Collins, CO · On-site

$108K - $172K/yr

Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating ...

Apple

SoC DFT Engineer

Austin, TX

$121K - $183K/yr

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Apple

SoC DFT Engineer

Austin, TX · On-site

As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and implementing ...

Google

IP DFT Engineer

Sunnyvale, CA · On-site

Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience. * 1 year of experience in DFT architecture, implementation, automatic test pattern ...

New

Broadcom

DFT Engineer

Irvine, CA · On-site

$108K - $192K/yr

Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools. * Perform ATPG and pattern simulation for both MBIST and scan. * Collaborate with the ...

E-Space

Senior DFT Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

E-Space

Senior DFT Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Apple

SoC DFT Engineer

Austin, TX · On-site

As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design.- Developing and implementing DFT ...

Apple

SoC DFT Engineer

Austin, TX · On-site

As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design.- Developing and implementing DFT ...

Broadcom, Inc.

DFT Engineer

San Jose, CA · On-site

$120K - $192K/yr

Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will ... Must be self-driven engineer with good project management and organizational skills to deliver high ...

Apple

SoC DFT Engineer

Austin, TX

$141K - $258K/yr

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Apple

SoC DFT Engineer

Austin, TX

$141K - $258K/yr

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Working closely with I/P DFT engineers and other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm and beyond

Apple

SoC DFT Engineer

Austin, TX

$172K - $305K/yr

Description As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Nokia

Principal SoC DFT Engineer

San Jose, CA · On-site

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group Responsibilities You will be working on DFT architecture and ...

Apple

SoC DFT Engineer

Austin, TX

$141K - $258K/yr

Description As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Apple

SoC DFT Engineer

Austin, TX

$172K - $305K/yr

Description As a DFT engineer we are involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

K2 Space

Senior DFT Engineer

Los Angeles, CA

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

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All JobsDft Engineer Jobs

Dft Engineer information

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$73K

$129.5K

$249K

How much do dft engineer jobs pay per year?

As of Jun 5, 2026, the average yearly pay for dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT Engineer, and why are they important?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within electronic design automation focused on designing chips that are easy to test. It offers steady demand in semiconductor and electronics industries, with opportunities for growth and skill development in areas like automation tools and verification techniques. Career prospects are generally favorable for those with strong technical skills and knowledge of testing methodologies.

What are some common challenges faced by DFT Engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What are DFT Engineers?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.
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Dft Engineer jobs near you
Infographic showing various Dft Engineer job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 67% In-person, and 33% Hybrid job distribution, with an average salary of $129,511 per year, or $62.3 per hour.
ASIC DFT Engineer

ASIC DFT Engineer

Broadcom, Inc.

Fort Collins, CO • On-site

$108K - $172K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 14 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 139 rated electronics manufacturers

Job description

Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for APD's designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.
Responsibilities:
  • Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
  • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
  • Candidate's primary responsibilities will be to verify and validate HBM & Die2Die IP's at ASIC level
  • Working closely with STA and DI Engineers design closure for test
  • Generating, Verifying & Debugging Test vectors before tape release.
  • Validating & Debugging Test vectors on ATE during the silicon bring up phase
  • Assisting with silicon failure analysis, diagnostics & yield improvement efforts
  • Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
  • Working closely with I/P DFT engineers & other stakeholders
  • Debugging customer returned parts on the ATE
  • Innovating newer DFT solutions to solve testability problems in 3nm & beyond
  • Automating DFT & Test Vector Generation flows

Skills/Experience:
  • Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
  • Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
  • Logic BIST design and debug experience
  • Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
  • Experience in Verilog coding, testbench generation & simulation
  • Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
  • Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
  • Basic knowledge Test-STA and constraints
  • Strong background on IEE1687, IJTAG, ICL and PDL
  • The ability to work in a multi-disciplined, cross-department environment
  • Solid knowledge in analog and digital circuit design, and device physics fundamentals
  • Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
  • Excellent problem solving, debug, root cause analysis and communication skills
  • Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics
  • Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.
  • Experience working on ATE is a plus
  • Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus
  • Experience working on Tessent SSN is a plus

Education & Experience:
  • Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience

Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $108,000 - $172,800.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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