Senior DFT Engineer
Santa Clara, CA · On-site
Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location: Santa Clara, CA We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA's high performance GPU and SoC ...
Senior DFT Engineer
Santa Clara, CA · On-site
Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location: Santa Clara, CA We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA's high performance GPU and SoC ...
Sr. DFT Engineer (Remote)
San Jose, CA · On-site
$122K - $168K/yr
Role: Sr. DFT Engineer Location: San Jose, CA-Remote Experience: 5+ Years Seeking Candidate Exposure with ATGP and SSM / SSN (Streaming Scan Network) developed by Siemens (Tessent) which Decouples ...
Quick apply
Sr. DFT Engineer (Remote)
San Jose, CA · On-site
$122K - $168K/yr
Role: Sr. DFT Engineer Location: San Jose, CA-Remote Experience: 5+ Years Seeking Candidate Exposure with ATGP and SSM / SSN (Streaming Scan Network) developed by Siemens (Tessent) which Decouples ...
Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG ...
Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG ...
Senior DFT Engineer
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
New
Senior DFT Engineer
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
New
Senior DFT Engineer
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
New
Quick apply
Senior DFT Engineer
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
New
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Senior DFT Engineer
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Senior DFT Engineer
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Senior DFT Engineer
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Quick apply
Senior DFT Engineer
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Senior DFT Engineer
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Senior DFT Engineer
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Senior DFT Engineer
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Senior DFT Engineer
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Senior DFT Engineer
Seattle, WA · On-site
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Senior DFT Engineer
Seattle, WA · On-site
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Senior DFT Engineer
Santa Clara, CA · On-site
$122K - $168K/yr
We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.
Senior DFT Engineer
Santa Clara, CA · On-site
$122K - $168K/yr
We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.
As a Senior DFT Engineer, you'll develop and implement powerful Design for Test (DFT) architecture for next-gen AI Chips. Collaborate with cross-functional teams to apply innovative DFT methodologies ...
As a Senior DFT Engineer, you'll develop and implement powerful Design for Test (DFT) architecture for next-gen AI Chips. Collaborate with cross-functional teams to apply innovative DFT methodologies ...
DFT Engineer
San Diego, CA · On-site
Role Description Sivaltech is seeking a highly skilled and experienced Senior DFT Engineer for a full-time, on-site position in the San Francisco Bay Area. In this role, you will be responsible for ...
DFT Engineer
San Diego, CA · On-site
Role Description Sivaltech is seeking a highly skilled and experienced Senior DFT Engineer for a full-time, on-site position in the San Francisco Bay Area. In this role, you will be responsible for ...
Senior DFT Engineer
Santa Clara, CA · Hybrid
$122K - $168K/yr
We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.
Senior DFT Engineer
Santa Clara, CA · Hybrid
$122K - $168K/yr
We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.
Senior DFT Engineer
Santa Clara, CA · On-site
$122K - $168K/yr
NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...
Senior DFT Engineer
Santa Clara, CA · On-site
$122K - $168K/yr
NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...
Senior DFT Engineer (Einfochips)
Tempe, AZ · On-site
$101K - $138K/yr
Senior DFT Engineer (Einfochips) What You'll Be Doing: * DFT implementation for 3nm and 5nm Networking chips, IP DFT work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan ...
Senior DFT Engineer (Einfochips)
Tempe, AZ · On-site
$101K - $138K/yr
Senior DFT Engineer (Einfochips) What You'll Be Doing: * DFT implementation for 3nm and 5nm Networking chips, IP DFT work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan ...
Senior DFT Engineer
Santa Clara, CA · Hybrid
$122K - $168K/yr
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...
Senior DFT Engineer
Santa Clara, CA · Hybrid
$122K - $168K/yr
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...
(6200-1021) Staff/Senior DFT Engineer
Santa Clara, CA · On-site
$130K - $174K/yr
Staff Senior DFT Engineer Requisition No.: 6200-1021 Department: Hardware Type of Position: Regular, Exempt Reports to: Director, Hardware Engineering Department: Hardware Engineering (US) Location:
(6200-1021) Staff/Senior DFT Engineer
Santa Clara, CA · On-site
$130K - $174K/yr
Staff Senior DFT Engineer Requisition No.: 6200-1021 Department: Hardware Type of Position: Regular, Exempt Reports to: Director, Hardware Engineering Department: Hardware Engineering (US) Location:
Senior DFT Engineer
Santa Clara, CA · Hybrid
$122K - $168K/yr
NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...
Senior DFT Engineer
Santa Clara, CA · Hybrid
$122K - $168K/yr
NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...
Senior Dft Engineer information
See salary details
$59.5K - $70.8K
1% of jobs
$70.8K - $82K
3% of jobs
$82K - $93.3K
7% of jobs
$104.4K is the 25th percentile. Wages below this are outliers.
$93.3K - $104.6K
14% of jobs
$104.6K - $115.9K
17% of jobs
The median wage is $120.6K / yr.
$115.9K - $127.1K
19% of jobs
$127.1K - $138.4K
13% of jobs
$139.8K is the 75th percentile. Wages above this are outliers.
$138.4K - $149.7K
11% of jobs
$149.7K - $161K
7% of jobs
$161K - $172.2K
5% of jobs
$172.2K - $183.5K
3% of jobs
$59.5K
$126.6K
$183.5K
How much do senior dft engineer jobs pay per year?
As of Jul 4, 2026, the average yearly pay for senior dft engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Senior DFT Engineer, and why are they important?
To thrive as a Senior DFT Engineer, you need deep expertise in digital design, test methodologies, and semiconductor fundamentals, typically supported by a degree in electrical or computer engineering and several years of related experience. Proficiency with EDA tools such as Synopsys Tetramax, Mentor Tessent, and scripting languages like Python or TCL is essential, alongside knowledge of industry standards like IEEE 1149.1 (JTAG). Strong analytical thinking, problem-solving abilities, and collaborative communication skills distinguish top performers in this role. These skills ensure robust test coverage, efficient debugging, and successful delivery of complex integrated circuits in high-stakes environments.
What are some common challenges Senior DFT Engineers face when integrating DFT methodologies into complex chip designs?
Senior DFT Engineers often encounter challenges such as balancing test coverage with minimal impact on area, performance, and power consumption. Integrating scan chains, boundary scan, and built-in self-test (BIST) requires close collaboration with RTL designers and verification teams to ensure testability features are implemented without introducing timing violations or design bottlenecks. Additionally, maintaining up-to-date knowledge of industry-standard DFT tools and methodologies, and managing tight project timelines while ensuring high-quality deliverables, are ongoing aspects of the role.
What are Senior DFT Engineers?
Senior DFT (Design for Test) Engineers are experienced professionals who specialize in designing and implementing testability features in integrated circuits (ICs) or systems-on-chip (SoCs). Their primary goal is to ensure that chips can be efficiently and thoroughly tested during manufacturing to detect and diagnose defects. They work on techniques such as scan insertion, built-in self-test (BIST), boundary scan, and test compression. Senior DFT Engineers typically collaborate with design, verification, and manufacturing teams to improve test coverage and reduce costs. Their expertise is crucial for delivering high-quality semiconductor products.
What is the difference between Senior Dft Engineer vs Dft Engineer?
| Aspect | Senior Dft Engineer | Dft Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electronics/Embedded Systems, relevant certifications | Bachelor's in Electronics/Embedded Systems, entry-level certifications |
| Work Environment | Design teams, manufacturing facilities, R&D labs | Design teams, manufacturing facilities |
| Employer & Industry Usage | Semiconductor, electronics manufacturing, automotive | Semiconductor, electronics manufacturing |
| Common Search & Comparison | Yes | Yes |
The main difference between a Senior Dft Engineer and a Dft Engineer lies in experience, responsibilities, and expertise. Senior Dft Engineers typically have more years of experience, lead complex DFT (Design for Test) projects, and mentor junior staff. Dft Engineers are often entry to mid-level professionals focused on executing DFT tasks under supervision. Both roles are vital in electronics manufacturing, but the senior position involves greater leadership and strategic planning.
More about Senior Dft Engineer jobs
What cities are hiring for Senior Dft Engineer jobs? Cities with the most Senior Dft Engineer job openings:
What states have the most Senior Dft Engineer jobs? States with the most job openings for Senior Dft Engineer jobs include:
What job categories do people searching Senior Dft Engineer jobs look for? The top searched job categories for Senior Dft Engineer jobs are:
Job description
Our client is looking Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] for Fulltime project in Santa Clara, CA (Onsite) Below is the detail requirement.
Job Title: Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification]
Location: Santa Clara, CA
Job Description:
We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA's high performance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with NVIDIA's cross functional teams to enable first time right silicon and high quality products.
Key Responsibilities
• Architect, implement, and validate DFT solutions to improve controllability and observability in complex GPU/SoC designs
• Lead scan-based DFT implementation, including scan insertion, compression, and test logic integration
• Develop and debug ATPG patterns targeting stuck at, transition, and additional fault models
• Implement and support MBIST architectures for on chip memory test, diagnosis, and coverage improvement
• Perform IO Test planning and validation to ensure reliable interface and pin level testing
• Support clock DFT and clock verification, including clock controllability, observability, and at speed test enablement
• Analyze fault coverage reports and drive improvements while balancing power, performance, and area constraints
• Collaborate closely with RTL, physical design, verification, and product engineering teams
• Support pattern simulation, silicon bring up, manufacturing test debug, and yield ramp
• Perform root cause analysis for test escapes and manufacturing failures
• Document DFT methodologies, test strategies, and best practices aligned with NVIDIA quality standards
Required Skills & Qualifications
• 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
• Proven expertise in ATPG pattern generation, analysis, and debug
• Experience with MBIST, including memory test architectures and diagnostics
• Knowledge of IO Test methodologies for interface and pin level validation
• Solid understanding of clock DFT and clock verification concepts
• Strong grasp of digital design and RTL fundamentals
• Experience with industry standard DFT/ATPG EDA tools
• Ability to work effectively in fast paced, high performance semiconductor programs
• Strong analytical, problem solving, and communication skills
Preferred Qualifications
• B-Tech , BE or equivalent degree in Electronics domain.
• Experience with silicon bring-up and production test support
• Exposure to advanced nodes and complex SoC & GPU architectures
• Exposure to low power and performance aware DFT techniques
• Experience supporting high volume production and yield optimization
• Knowledge of low-power and performance-aware DFT techniques
• Experience working in high-volume manufacturing environments
Job Title: Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification]
Location: Santa Clara, CA
Job Description:
We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA's high performance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with NVIDIA's cross functional teams to enable first time right silicon and high quality products.
Key Responsibilities
• Architect, implement, and validate DFT solutions to improve controllability and observability in complex GPU/SoC designs
• Lead scan-based DFT implementation, including scan insertion, compression, and test logic integration
• Develop and debug ATPG patterns targeting stuck at, transition, and additional fault models
• Implement and support MBIST architectures for on chip memory test, diagnosis, and coverage improvement
• Perform IO Test planning and validation to ensure reliable interface and pin level testing
• Support clock DFT and clock verification, including clock controllability, observability, and at speed test enablement
• Analyze fault coverage reports and drive improvements while balancing power, performance, and area constraints
• Collaborate closely with RTL, physical design, verification, and product engineering teams
• Support pattern simulation, silicon bring up, manufacturing test debug, and yield ramp
• Perform root cause analysis for test escapes and manufacturing failures
• Document DFT methodologies, test strategies, and best practices aligned with NVIDIA quality standards
Required Skills & Qualifications
• 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
• Proven expertise in ATPG pattern generation, analysis, and debug
• Experience with MBIST, including memory test architectures and diagnostics
• Knowledge of IO Test methodologies for interface and pin level validation
• Solid understanding of clock DFT and clock verification concepts
• Strong grasp of digital design and RTL fundamentals
• Experience with industry standard DFT/ATPG EDA tools
• Ability to work effectively in fast paced, high performance semiconductor programs
• Strong analytical, problem solving, and communication skills
Preferred Qualifications
• B-Tech , BE or equivalent degree in Electronics domain.
• Experience with silicon bring-up and production test support
• Exposure to advanced nodes and complex SoC & GPU architectures
• Exposure to low power and performance aware DFT techniques
• Experience supporting high volume production and yield optimization
• Knowledge of low-power and performance-aware DFT techniques
• Experience working in high-volume manufacturing environments
About Lorven technologies
Sourced by ZipRecruiter
Lorven Technologies, headquartered in Plainsboro, New Jersey, United States, is a reputable company in the technology industry, specializing in providing effective IT solutions and consulting services. The company's official website, lorventech.com, offers comprehensive insights into its offerings which include but are not limited to software development, IT consulting, project management, and business analysis. Since its inception, Lorven Technologies has been committed to ensuring efficiency and reliability in delivering IT services to its global clientele, establishing itself as a trusted name in the industry.
Industry
It services
Company size
51 - 200 Employees
Headquarters location
Plainsboro, NJ, US
Year founded
2001