ZipRecruiter

Log In

1

Senior Dft Engineer Jobs (NOW HIRING)

Phizenix

Staff DFT Engineer

Santa Clara, CA

$130K - $180K/yr

What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, CA

$155K - $185K/yr

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

Mirafra Technology

DFT Engineer

Tempe, AZ

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Need knowledge of design for test (DFT) structures such as scan chains ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Austin, TX

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA

$145K - $175K/yr

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Austin, TX · On-site

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA · On-site

$145K - $175K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, CA

$155K - $185K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, CA · On-site

$155K - $185K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

Nokia

Principal SoC DFT Engineer

San Jose, CA · On-site

As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design and product engineers to achieve first pass silicon success. Perform hands-on DFT ...

Nokia

Principal SoC DFT Engineer

San Jose, CA

As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design and product engineers to achieve first pass silicon success. Perform hands-on DFT ...

Tesla

Sr. DFT Verification Engineer, AI Hardware

Austin, TX · On-site

$109K - $146K/yr

Tesla's AI Hardware team is looking for a Design-for-Test (DFT) Design Verification Engineer to work on custom ASICs. You will drive state of the art in the area of testability and contribute to ...

New

next page

Showing results 1-20

People also search for

All JobsSenior Dft Engineer Jobs

Senior Dft Engineer information

See salary details

$59.5K

$126.6K

$183.5K

How much do senior dft engineer jobs pay per year?

As of Jun 6, 2026, the average yearly pay for senior dft engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Senior DFT Engineer, and why are they important?

To thrive as a Senior DFT Engineer, you need deep expertise in digital design, test methodologies, and semiconductor fundamentals, typically supported by a degree in electrical or computer engineering and several years of related experience. Proficiency with EDA tools such as Synopsys Tetramax, Mentor Tessent, and scripting languages like Python or TCL is essential, alongside knowledge of industry standards like IEEE 1149.1 (JTAG). Strong analytical thinking, problem-solving abilities, and collaborative communication skills distinguish top performers in this role. These skills ensure robust test coverage, efficient debugging, and successful delivery of complex integrated circuits in high-stakes environments.

What are some common challenges Senior DFT Engineers face when integrating DFT methodologies into complex chip designs?

Senior DFT Engineers often encounter challenges such as balancing test coverage with minimal impact on area, performance, and power consumption. Integrating scan chains, boundary scan, and built-in self-test (BIST) requires close collaboration with RTL designers and verification teams to ensure testability features are implemented without introducing timing violations or design bottlenecks. Additionally, maintaining up-to-date knowledge of industry-standard DFT tools and methodologies, and managing tight project timelines while ensuring high-quality deliverables, are ongoing aspects of the role.

What are Senior DFT Engineers?

Senior DFT (Design for Test) Engineers are experienced professionals who specialize in designing and implementing testability features in integrated circuits (ICs) or systems-on-chip (SoCs). Their primary goal is to ensure that chips can be efficiently and thoroughly tested during manufacturing to detect and diagnose defects. They work on techniques such as scan insertion, built-in self-test (BIST), boundary scan, and test compression. Senior DFT Engineers typically collaborate with design, verification, and manufacturing teams to improve test coverage and reduce costs. Their expertise is crucial for delivering high-quality semiconductor products.

What is the difference between Senior Dft Engineer vs Dft Engineer?

AspectSenior Dft EngineerDft Engineer
Required CredentialsBachelor's or Master's in Electronics/Embedded Systems, relevant certificationsBachelor's in Electronics/Embedded Systems, entry-level certifications
Work EnvironmentDesign teams, manufacturing facilities, R&D labsDesign teams, manufacturing facilities
Employer & Industry UsageSemiconductor, electronics manufacturing, automotiveSemiconductor, electronics manufacturing
Common Search & ComparisonYesYes

The main difference between a Senior Dft Engineer and a Dft Engineer lies in experience, responsibilities, and expertise. Senior Dft Engineers typically have more years of experience, lead complex DFT (Design for Test) projects, and mentor junior staff. Dft Engineers are often entry to mid-level professionals focused on executing DFT tasks under supervision. Both roles are vital in electronics manufacturing, but the senior position involves greater leadership and strategic planning.

What cities are hiring for Senior Dft Engineer jobs? Cities with the most Senior Dft Engineer job openings:
What states have the most Senior Dft Engineer jobs? States with the most job openings for Senior Dft Engineer jobs include:
Senior Dft Engineer jobs near you
Infographic showing various Senior Dft Engineer job openings in the United States as of May 2026, with employment types broken down into 17% As Needed, 17% Full Time, 17% Part Time, and 49% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $126,557 per year, or $60.8 per hour.

Staff DFT Engineer

Phizenix

Santa Clara, CA

$130K - $180K/yr

Full-time

Posted yesterday

Job description

What You Can Expect
We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role focuses on end-to-end scan execution, from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own scan quality, coverage closure, and DFT signoff for complex SoC designs.

ESSENTIAL DUTIES AND RESPONSIBILITIES
Lead hands-on scan DFT implementation, including:Scan insertion and stitching
Scan Streaming Network (SSN) implementation
IJTAG (IEEE 1687) insertion and connectivity

Perform scan DFT verification, debug, and DFT DRC closure
Debug and resolve scan-related DRCs, connectivity issues, and control signal problems
Run, analyze, and debug SpyGlass DFT/RTL checks, partnering with design teams to resolve violations
Generate, simulate, and debug ATPG scan patterns
Analyze ATPG results and drive scan coverage improvement and closure
Develop and validate DFT-related timing constraints (scan, shift, capture, and test modes)
Create and maintain TCL scripts for scan insertion, ATPG setup, and coverage analysis
Optimize scan implementations for pattern efficiency and test quality
Support hierarchical scan integration at both block and SoC levels
Collaborate closely with RTL and Physical Design teams to resolve scan-related issues
Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug
Assist with ATE pattern conversion and scan debug activities

What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or
related fields and 5-10 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or
related fields with 3-5 years of experience.
8+ years of hands-on experience in DFT scan implementation
Strong expertise with Siemens Tessent, including:Scan insertion and verification
ATPG pattern generation and coverage analysis
IJTAG (IEEE 1687) and SSN implementation

Strong understanding of:Scan Streaming Network (SSN)
IEEE 1149.x, IEEE 1500, and IEEE 1687 standards

Proven ability to resolve scan DFT DRCs and drive coverage closure
Strong TCL scripting skills for automation and flow customization
Experience developing and validating scan and test-mode timing constraints
Full DFT lifecycle experience, from RTL/netlist through silicon debug
Strong debugging, ownership, and problem-solving skills
Excellent verbal and written communication skills

PREFERRED QUALIFICATIONS
Experience with scan compression and advanced scan architectures
Post-silicon experience, including:Pattern bring-up and debug
Silicon characterization and yield learning

Experience mentoring junior engineers or owning DFT scan signoff

California Pay Range
$130,000—$180,000 USD