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Senior Dft Engineer Jobs (NOW HIRING)

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.

Sr. DFT Engineer, AI Hardware

Austin, TX ยท On-site

$109K - $146K/yr

Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference ... Work closelywith the physical design team in achievingdesign closure with DFT features * Perform ...

Role :- Senior ASIC DFT CDC Constraints Eng Location :- San Jose, CA/Milpitas, CA (Remote) Type ... Work with ATPG engineers (Tessent / Synopsys DFTC) to validate that test patterns respect CDC ...

Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...

What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role ...

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, CA ยท On-site

$155K - $185K/yr

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

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Senior Dft Engineer information

See salary details

$59.5K

$126.6K

$183.5K

How much do senior dft engineer jobs pay per year?

As of Jun 6, 2026, the average yearly pay for senior dft engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Senior DFT Engineer, and why are they important?

To thrive as a Senior DFT Engineer, you need deep expertise in digital design, test methodologies, and semiconductor fundamentals, typically supported by a degree in electrical or computer engineering and several years of related experience. Proficiency with EDA tools such as Synopsys Tetramax, Mentor Tessent, and scripting languages like Python or TCL is essential, alongside knowledge of industry standards like IEEE 1149.1 (JTAG). Strong analytical thinking, problem-solving abilities, and collaborative communication skills distinguish top performers in this role. These skills ensure robust test coverage, efficient debugging, and successful delivery of complex integrated circuits in high-stakes environments.

What are some common challenges Senior DFT Engineers face when integrating DFT methodologies into complex chip designs?

Senior DFT Engineers often encounter challenges such as balancing test coverage with minimal impact on area, performance, and power consumption. Integrating scan chains, boundary scan, and built-in self-test (BIST) requires close collaboration with RTL designers and verification teams to ensure testability features are implemented without introducing timing violations or design bottlenecks. Additionally, maintaining up-to-date knowledge of industry-standard DFT tools and methodologies, and managing tight project timelines while ensuring high-quality deliverables, are ongoing aspects of the role.

What are Senior DFT Engineers?

Senior DFT (Design for Test) Engineers are experienced professionals who specialize in designing and implementing testability features in integrated circuits (ICs) or systems-on-chip (SoCs). Their primary goal is to ensure that chips can be efficiently and thoroughly tested during manufacturing to detect and diagnose defects. They work on techniques such as scan insertion, built-in self-test (BIST), boundary scan, and test compression. Senior DFT Engineers typically collaborate with design, verification, and manufacturing teams to improve test coverage and reduce costs. Their expertise is crucial for delivering high-quality semiconductor products.

What is the difference between Senior Dft Engineer vs Dft Engineer?

AspectSenior Dft EngineerDft Engineer
Required CredentialsBachelor's or Master's in Electronics/Embedded Systems, relevant certificationsBachelor's in Electronics/Embedded Systems, entry-level certifications
Work EnvironmentDesign teams, manufacturing facilities, R&D labsDesign teams, manufacturing facilities
Employer & Industry UsageSemiconductor, electronics manufacturing, automotiveSemiconductor, electronics manufacturing
Common Search & ComparisonYesYes

The main difference between a Senior Dft Engineer and a Dft Engineer lies in experience, responsibilities, and expertise. Senior Dft Engineers typically have more years of experience, lead complex DFT (Design for Test) projects, and mentor junior staff. Dft Engineers are often entry to mid-level professionals focused on executing DFT tasks under supervision. Both roles are vital in electronics manufacturing, but the senior position involves greater leadership and strategic planning.

What cities are hiring for Senior Dft Engineer jobs? Cities with the most Senior Dft Engineer job openings:
What states have the most Senior Dft Engineer jobs? States with the most job openings for Senior Dft Engineer jobs include:
Infographic showing various Senior Dft Engineer job openings in the United States as of May 2026, with employment types broken down into 17% As Needed, 17% Full Time, 17% Part Time, and 49% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $126,557 per year, or $60.8 per hour.
Senior DFT Engineer

Senior DFT Engineer

Nvidia

Santa Clara, CA โ€ข Hybrid

$122K - $168K/yr

Full-time

This job post hasย expired today.ย Applications are no longer accepted.


Job description

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work , to amplify human imagination and intelligence. Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

  • As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.

  • In addition, you will help develop and deploy DFT methodologies for our next generation products.

  • You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

  • BSEE (or equivalent experience) with 5+, MSEE with 3+ years of experience or PhD in DFT or related domains

  • Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation

  • Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools

  • Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs

  • Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development

  • Strong programming and scripting skills in Perl, Python or Tcl desired

  • Extraordinary written and oral communication skills with the curiosity to work on rare challenges

Our technology has no boundaries! NVIDIA is building the world's most groundbreaking and state of the art compute platforms for the world to use. It's because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an outstanding computing experience, but it is also energy efficient! We pioneered a supercharged form of computing loved by the most demanding computer users in the world - scientists, designers, artists, and gamers.

NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 8, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Nvidia logo

About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993