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Dft Engineer Jobs (NOW HIRING)

Job Title: DFT Engineer Location: Santa Clara, CA Role Purpose: We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key Responsibilities: * Work on Scan ...

DFT Engineer Location:Santa Clara CA Duration:Long term Experience:8-15 Years Role Purpose We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key ...

Job Title: DFT Engineer Location: Santa Clara, CA Role Purpose: We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key Responsibilities: Work on Scan ...

DFT Engineer

Santa Clara, UT · On-site

$100K - $180K/yr

DFT Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...

DFT Engineer Location: San Jose, CA, Fort Collins, CO, Allentown, PA, Irvine, CA, Minneapolis, MN. Duration: Full-time/Perm Client's ASIC Product Division is seeking candidates for a DFT Lead ...

DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for ...

DFT Engineer

Santa Clara, UT · On-site

$60K - $148K/yr

DFT Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...

DFT Engineer DFT Engineer will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE). MMEDE BU brings the technology and ecosystem ...

New

DFT Engineer

Richardson, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Contribute to sign-off checklist and tapeout readiness reviews for timing and DFT closure * Mentor mid-level engineers on CDC-aware constraint methodology and scan-mode timing analysis * Engage with ...

Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location: Santa Clara, CA We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA's high performance GPU and SoC ...

Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location: Santa Clara, CA We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA's high performance GPU and SoC ...

DFT Engineer Responsibilities * Define & document DFT requirements/Specifications for IP/Block and Chip level * Execute DFT Lint to identify scan DRC violations and resolution * Top level and hard ...

SoC Dft Engineer Work Locations (3) Submit Resume Do you love crafting sophisticated solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As part of ...

DFT Engineer

San Jose, CA · On-site

$120K - $192K/yr

Working closely with I/P DFT engineers and other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm and beyond

What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role ...

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Dft Engineer information

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$73K

$129.5K

$249K

How much do dft engineer jobs pay per year?

As of Jun 5, 2026, the average yearly pay for dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT Engineer, and why are they important?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within electronic design automation focused on designing chips that are easy to test. It offers steady demand in semiconductor and electronics industries, with opportunities for growth and skill development in areas like automation tools and verification techniques. Career prospects are generally favorable for those with strong technical skills and knowledge of testing methodologies.

What are some common challenges faced by DFT Engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What are DFT Engineers?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.
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Infographic showing various Dft Engineer job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 67% In-person, and 33% Hybrid job distribution, with an average salary of $129,511 per year, or $62.3 per hour.
DFT Engineer

Other

Posted 3 days ago


Job description

Job Title: DFT Engineer
Location: Santa Clara, CA
Role Purpose:
We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan
Key Responsibilities:
  • Work on Scan insertion, ATPG, GLS (timing/non-timing)
  • Implement MBIST and/or Boundary Scan (BSCAN, JTAG)
  • Support DFT architecture and chip-level integration
  • Debug DFT issues and improve test coverage

Requirements:
  • Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS)
  • Strong understanding of DFT concepts and flow
  • Exposure to end-to-end DFT is a plus