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Dft Engineer Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior DFT Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

K2 Space

Senior DFT Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

K2 Space

Senior DFT Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

K2 Space

Senior DFT Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

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All JobsDft Engineer JobsDft Engineer Jobs in Seattle, WA

Dft Engineer information

See Seattle, WA salary details

$83.1K

$147.4K

$283.4K

How much do dft engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for dft engineer in Seattle, WA is $147,387.00, according to ZipRecruiter salary data. Most workers in this role earn between $117,200.00 and $153,100.00 per year, depending on experience, location, and employer.

What is a DFT engineer?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.

What are the key skills and qualifications needed to thrive as a DFT engineer?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering in demand?

DFT (Design for Test) engineering is in demand within the semiconductor and integrated circuit industries, as companies seek to improve chip testability and reduce manufacturing costs. Skills in digital design, verification, and familiarity with EDA tools are valuable, and demand is driven by ongoing advancements in electronics and increasing complexity of chips.

What are popular job titles related to Dft Engineer jobs in Seattle, WA?

For Dft Engineer jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Dft Engineer jobs in Seattle, WA look for?

The top searched job categories for Dft Engineer jobs in Seattle, WA are:

Dft Engineer jobs near you
Infographic showing various Dft Engineer job openings in Seattle, WA as of August 2026, with employment types broken down into 91% Full Time, 4% Part Time, and 5% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $147,387 per year, or $70.9 per hour.

Senior DFT Engineer

K2 Space

Seattle, WA • On-site

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 17 days ago

Job description

The Role 

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.  

Responsibilities 

  • Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. 
  • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. 
  • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.  
  • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. 
  • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). 
  • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. 
  • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. 
  • Contribute to methodology development, automation, and flow improvements. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering or related field. 
  • 7+ years of experience in DFT for complex SoCs. 
  • Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. 
  • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. 
  • Experience with low-power DFT techniques. 
  • Familiarity with mixed-signal integration challenges and test methodologies. 
  • Strong debugging skills across RTL, gate-level, and silicon. 

Nice to Have 

  • Experience with MBIST/LBIST implementation and memory repair flows. 
  • Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. 
  • Experience with multi-voltage domain and power-aware DFT. 
  • Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). 
  • Scripting experience for automation. 
  • Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. 
  • Prior involvement in A0 silicon bring-up and yield ramp. 
  • Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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