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Senior Dft Engineer Jobs in Oregon (NOW HIRING)

K2 Space

Senior DFT Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Addium Inc

Senior Electrical Engineer

Portland, OR · On-site

$130K - $140K/yr

Senior Electrical Engineer Department: Product Development: Hardware Reports To: Director of ... Partner with contract manufacturers on DFM/DFT reviews and drive designs through EVT, DVT, and PVT ...

K2 Space

Senior ASIC Design Verification Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable ...

Actalent

PCB Design Engineer

Tualatin, OR

Sr. PCB Design Engineer --- This Sr. PCB Design Engineer role focuses on end-to-end development of ... Collaborate with design-for-test (DFT) engineers to resolve test access issues and ensure robust ...

K2 Space

Senior FPGA Prototyping Engineer

OR · On-site +1

$120K - $225K/yr

The Role We are seeking a Senior FPGA & Silicon Bring-up Engineer to accelerate the development of ... Collaborate closely with ASIC Design, Verification, Firmware, Software, Systems, and DFT teams to ...

New

Microsoft

Senior Physical Design Engineer

Hillsboro, OR · On-site

$113K - $156K/yr

We are looking for a Senior Physical Design Engineer to join the team. #SCHIE #CSME ... Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment ... You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ...

Nvidia

Senior ASIC Timing Engineer

Hillsboro, OR · Hybrid

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan ...

Nvidia

OR · Hybrid

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive ... Understanding of DFT/IST is optional. What to Stand Out From the Crowd: - * Previous experience ...

Ralliant

Hardware Design Engineer

Beaverton, OR · On-site

Support PCB layout activities by working with senior engineers to define component placement ... Knowledge of Design for Manufacturability (DFM) and Design for Testability (DFT) principles.

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All JobsDft Engineer JobsSenior Dft Engineer JobsSenior Dft Engineer Jobs in Oregon

Senior Dft Engineer information

See Oregon salary details

$62.9K

$133.8K

$194K

How much do senior dft engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for senior dft engineer in Oregon is $133,807.00, according to ZipRecruiter salary data. Most workers in this role earn between $110,500.00 and $151,700.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Senior DFT engineer, and why are they important?

To thrive as a Senior DFT Engineer, you need deep expertise in digital design, test methodologies, and semiconductor fundamentals, typically supported by a degree in electrical or computer engineering and several years of related experience. Proficiency with EDA tools such as Synopsys Tetramax, Mentor Tessent, and scripting languages like Python or TCL is essential, alongside knowledge of industry standards like IEEE 1149.1 (JTAG). Strong analytical thinking, problem-solving abilities, and collaborative communication skills distinguish top performers in this role. These skills ensure robust test coverage, efficient debugging, and successful delivery of complex integrated circuits in high-stakes environments.

What are some common challenges Senior DFT engineers face when integrating DFT methodologies into complex chip designs?

Senior DFT Engineers often encounter challenges such as balancing test coverage with minimal impact on area, performance, and power consumption. Integrating scan chains, boundary scan, and built-in self-test (BIST) requires close collaboration with RTL designers and verification teams to ensure testability features are implemented without introducing timing violations or design bottlenecks. Additionally, maintaining up-to-date knowledge of industry-standard DFT tools and methodologies, and managing tight project timelines while ensuring high-quality deliverables, are ongoing aspects of the role.

What is a Senior DFT engineer?

Senior DFT (Design for Test) Engineers are experienced professionals who specialize in designing and implementing testability features in integrated circuits (ICs) or systems-on-chip (SoCs). Their primary goal is to ensure that chips can be efficiently and thoroughly tested during manufacturing to detect and diagnose defects. They work on techniques such as scan insertion, built-in self-test (BIST), boundary scan, and test compression. Senior DFT Engineers typically collaborate with design, verification, and manufacturing teams to improve test coverage and reduce costs. Their expertise is crucial for delivering high-quality semiconductor products.

What is the difference between Senior Dft Engineer vs Dft Engineer?

AspectSenior Dft EngineerDft Engineer
Required CredentialsBachelor's or Master's in Electronics/Embedded Systems, relevant certificationsBachelor's in Electronics/Embedded Systems, entry-level certifications
Work EnvironmentDesign teams, manufacturing facilities, R&D labsDesign teams, manufacturing facilities
Employer & Industry UsageSemiconductor, electronics manufacturing, automotiveSemiconductor, electronics manufacturing
Common Search & ComparisonYesYes

The main difference between a Senior Dft Engineer and a Dft Engineer lies in experience, responsibilities, and expertise. Senior Dft Engineers typically have more years of experience, lead complex DFT (Design for Test) projects, and mentor junior staff. Dft Engineers are often entry to mid-level professionals focused on executing DFT tasks under supervision. Both roles are vital in electronics manufacturing, but the senior position involves greater leadership and strategic planning.

What are popular job titles related to Senior Dft Engineer jobs in Oregon?

For Senior Dft Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Senior Dft Engineer jobs in Oregon look for?

The top searched job categories for Senior Dft Engineer jobs in Oregon are:

What cities in Oregon are hiring for Senior Dft Engineer jobs?

Cities in Oregon with the most Senior Dft Engineer job openings:

Senior Dft Engineer jobs near you
Infographic showing various Senior Dft Engineer job openings in Oregon as of August 2026, with employment types broken down into 87% Full Time, 6% Part Time, 6% Contract, and 1% Nights. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $133,807 per year, or $64.3 per hour.

Senior DFT Engineer

K2 Space

OR • On-site, Remote

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 15 days ago

Job description

The Role 

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.  

Responsibilities 

  • Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. 
  • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. 
  • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.  
  • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. 
  • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). 
  • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. 
  • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. 
  • Contribute to methodology development, automation, and flow improvements. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering or related field. 
  • 7+ years of experience in DFT for complex SoCs. 
  • Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. 
  • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. 
  • Experience with low-power DFT techniques. 
  • Familiarity with mixed-signal integration challenges and test methodologies. 
  • Strong debugging skills across RTL, gate-level, and silicon. 

Nice to Have 

  • Experience with MBIST/LBIST implementation and memory repair flows. 
  • Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. 
  • Experience with multi-voltage domain and power-aware DFT. 
  • Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). 
  • Scripting experience for automation. 
  • Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. 
  • Prior involvement in A0 silicon bring-up and yield ramp. 
  • Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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