Senior Dft Engineer Jobs in Virginia (NOW HIRING)

Bristol

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are seeking a senior Semiconductor Product Engineering leader to drive manufacturing test strategy and silicon production readiness for next‑generation AI accelerator devices. This role combines deep technical expertise in high‑performance compute silicon with leadership responsibility for internal product engineering teams and external development partners. The successful candidate will oversee all aspects of production test development — from DFT strategy and ATE bring‑up through silicon characterization, yield optimization, advanced packaging test, and high‑volume manufacturing ramp — ensuring robust, scalable, and cost‑effective test solutions for advanced AI accelerator platforms.

• Drive the manufacturing test strategy for an AI accelerator chip featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and advanced packaging (e.g., 2.5D/3D, chiplet).
• Lead and manage a team of chip product engineers responsible for test planning, test program development, pattern bring‑up, silicon characterization, debug, and optimization.
• Manage subcontracted test development partners (OSATs, ATE vendors, external engineering services). Includes scoping, technical oversight, schedule tracking, and quality control of deliverables.
• Define and drive test software architecture, DFT usage, and test pattern development strategies for high‑speed logic, SRAM, DRAM, and high‑speed IO blocks.
• Work closely with design, DFT, manufacturing engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success.
• Oversee test development for high speed interfaces such as PCIe Gen6 and multi‑GHz LPDDR.
• Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system‑level tests).
• Lead silicon bring‑up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities.
• Define KPIs and metrics for subcontractor performance, test coverage, yield, time‑to‑test, and cost optimization.
• Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure.
• Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die‑to‑die IO testing).
• Support qualification, reliability testing, and high‑volume manufacturing transfer.

• BS/MS/PhD in Electronics and Electrical Engineering or related field.
• 8+ years in semiconductor test engineering, including leadership or technical lead roles.
• Experience with ATE test development (e.g., Advantest 93K, Teradyne Ultraflex or similar).
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high‑speed interface testing.
• Experience managing external test development partners or OSATs.
• Proven ability to lead and mentor test engineering teams.
• Solid background in advanced CMOS nodes and familiarity with advanced packaging test challenges.
• Expertise in silicon debug, characterization, and correlation across ATE and system‑level environments.
• Ability to collaborate across design, architecture, product engineering, packaging, and operations.

• Experience with AI/ML accelerator chips or other high‑performance compute ICs.
• Prior involvement with PCIe Gen5/Gen6 or LPDDR4/5/6 test methodologies.
• Familiarity with signal‑integrity-aware test development and high‑speed IO margining.
• Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.