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Senior Dft Engineer Jobs in California (NOW HIRING)

Sr. DFT Engineer (Remote)

San Jose, CA ยท On-site

$122K - $168K/yr

Role: Sr. DFT Engineer Location: San Jose, CA-Remote Experience: 5+ Years Seeking Candidate Exposure with ATGP and SSM / SSN (Streaming Scan Network) developed by Siemens (Tessent) which Decouples ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding ...

Senior DFT Engineer

Saratoga, CA ยท On-site

$120 - $220/hr

  • Medical

  • PTO

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Senior DFT Engineer

Saratoga, CA ยท On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Senior DFT Engineer

Saratoga, CA ยท On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Senior DFT Engineer

Saratoga, CA ยท On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Senior DFT Engineer (Einfochips)

San Jose, CA ยท On-site

$122K - $168K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Senior DFT Engineer (Einfochips) What You'll Be Doing: * DFT implementation for 3nm and 5nm Networking chips, IP DFT work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$121K - $167K/yr

We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today.

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in ...

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

Senior DFT Engineer

Santa Clara, CA ยท Hybrid

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

Senior DFT Engineer

Santa Clara, CA ยท On-site

$122K - $168K/yr

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry ...

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Showing results 1-20

Senior Dft Engineer information

See California salary details

$58.7K

$124.9K

$181.1K

How much do senior dft engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for senior dft engineer in California is $124,900.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,100.00 and $141,600.00 per year, depending on experience, location, and employer.

What is a Senior DFT engineer?

Senior DFT (Design for Test) Engineers are experienced professionals who specialize in designing and implementing testability features in integrated circuits (ICs) or systems-on-chip (SoCs). Their primary goal is to ensure that chips can be efficiently and thoroughly tested during manufacturing to detect and diagnose defects. They work on techniques such as scan insertion, built-in self-test (BIST), boundary scan, and test compression. Senior DFT Engineers typically collaborate with design, verification, and manufacturing teams to improve test coverage and reduce costs. Their expertise is crucial for delivering high-quality semiconductor products.

What are some common challenges Senior DFT engineers face when integrating DFT methodologies into complex chip designs?

Senior DFT Engineers often encounter challenges such as balancing test coverage with minimal impact on area, performance, and power consumption. Integrating scan chains, boundary scan, and built-in self-test (BIST) requires close collaboration with RTL designers and verification teams to ensure testability features are implemented without introducing timing violations or design bottlenecks. Additionally, maintaining up-to-date knowledge of industry-standard DFT tools and methodologies, and managing tight project timelines while ensuring high-quality deliverables, are ongoing aspects of the role.

What are the key skills and qualifications needed to thrive as a Senior DFT engineer, and why are they important?

To thrive as a Senior DFT Engineer, you need deep expertise in digital design, test methodologies, and semiconductor fundamentals, typically supported by a degree in electrical or computer engineering and several years of related experience. Proficiency with EDA tools such as Synopsys Tetramax, Mentor Tessent, and scripting languages like Python or TCL is essential, alongside knowledge of industry standards like IEEE 1149.1 (JTAG). Strong analytical thinking, problem-solving abilities, and collaborative communication skills distinguish top performers in this role. These skills ensure robust test coverage, efficient debugging, and successful delivery of complex integrated circuits in high-stakes environments.

What is the difference between Senior Dft Engineer vs Dft Engineer?

AspectSenior Dft EngineerDft Engineer
Required CredentialsBachelor's or Master's in Electronics/Embedded Systems, relevant certificationsBachelor's in Electronics/Embedded Systems, entry-level certifications
Work EnvironmentDesign teams, manufacturing facilities, R&D labsDesign teams, manufacturing facilities
Employer & Industry UsageSemiconductor, electronics manufacturing, automotiveSemiconductor, electronics manufacturing
Common Search & ComparisonYesYes

The main difference between a Senior Dft Engineer and a Dft Engineer lies in experience, responsibilities, and expertise. Senior Dft Engineers typically have more years of experience, lead complex DFT (Design for Test) projects, and mentor junior staff. Dft Engineers are often entry to mid-level professionals focused on executing DFT tasks under supervision. Both roles are vital in electronics manufacturing, but the senior position involves greater leadership and strategic planning.

What job categories do people searching Senior Dft Engineer jobs in California look for?

The top searched job categories for Senior Dft Engineer jobs in California are:

What cities in California are hiring for Senior Dft Engineer jobs?

Cities in California with the most Senior Dft Engineer job openings:

Infographic showing various Senior Dft Engineer job openings in California as of August 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution, with an average salary of $124,900 per year, or $60 per hour.

Sr. DFT Engineer (Remote)

Siri InfoSolutions Inc

San Jose, CA โ€ข On-site

$122K - $168K/yr

Contractor

Re-posted 19 days ago


Job description

Role: Sr. DFT Engineer

Location: San Jose, CA-Remote

Experience: 5+ Years

Seeking Candidate Exposure with ATGP and SSM / SSN (Streaming Scan Network) developed by Siemens (Tessent) which Decouples Core (Block) and Chip

What You'll Be Doing:

• Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level

• Verify test patterns using gate-level simulations.

• Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT related problems.

• Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing.

What We Are Looking For:

• Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG,  and MBIST.

• Proven experience in developing DFT specifications and architectures for complex designs.

• Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more.

• Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification.

• Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes.

• Efficient scripting skills using TCL for automating tasks and developing custom flows.

Education: Bachelor’s degree

Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.


Siri Infosolutions logo

About Siri Infosolutions

Sourced by ZipRecruiter

Our team of experts first gather each and every requirement of yours. Our research and development team then sit around those requirements and come up with a plan. Our implementation team then executes that plan for optimal results. After that our support team remains in constant touch with you during and after the entire process.

Industry

It services

Company size

201 - 500 Employees

Headquarters location

Edison, NJ, US

Year founded

2005