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Contract Uvm Verification Jobs (NOW HIRING)

Amarx Search, Inc.

Senior FPGA Engineer

Cincinnati, OH

$106K - $197K/yr

... government contract requirements We can ONLY consider your application if you have: 1: Bachelor ... Knowledge using SystemVerilog for verification with AVM, VMM, OVM, or UVM a plus. :: Developing C# ...

Chipton Ross

FPGA Design Engineer

Sunnyvale, CA · On-site

$144K - $198K/yr

Job #216829 Chipton-Ross is seeking an FPGA Design Engineer for a contract opportunity in Sunnyvale ... Verifying FPGA and/or ASIC designs including creating UVM verification environments, testbenches ...

Mythic

Senior Design Verification Engineer

Austin, TX

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Senior Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Senior Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Senior Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Austin, TX

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Palo Alto, CA

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Palo Alto, CA

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Austin, TX

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

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All JobsContract Uvm Verification Jobs

Contract Uvm Verification information

See salary details

$80K

$142.6K

$203.5K

How much do contract uvm verification jobs pay per year?

As of Jun 9, 2026, the average yearly pay for contract uvm verification in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Contract Uvm Verification vs Contract SystemVerilog Verification?

AspectContract Uvm VerificationContract SystemVerilog Verification
CredentialsUVM Certification, Verilog/SystemVerilog knowledgeVerilog/SystemVerilog expertise, verification certifications
Work EnvironmentASIC/FPGA verification teams, EDA toolsASIC/FPGA verification teams, EDA tools
Industry UsageCommon in UVM-based verification environmentsUsed broadly in SystemVerilog verification projects
Comparison FocusUVM methodology specificsSystemVerilog language features

Contract Uvm Verification primarily focuses on UVM methodology and testbench development, while Contract SystemVerilog Verification emphasizes proficiency in SystemVerilog language features for verification tasks. Both roles often overlap but differ in their core focus areas within the verification process.

What are some common challenges faced by Contract UVM Verification engineers when joining new projects, and how can they be addressed?

Contract UVM Verification engineers often face challenges such as quickly ramping up on unfamiliar codebases, understanding project-specific verification methodologies, and integrating with established teams. To overcome these, it’s important to proactively communicate with team members, thoroughly review project documentation, and leverage reusable UVM components where possible. Establishing strong lines of communication and participating in regular sync meetings can help bridge knowledge gaps and ensure alignment with project goals.

What are Contract UVM Verification engineers?

Contract UVM Verification engineers are professionals who specialize in using the Universal Verification Methodology (UVM) to verify the functionality of digital hardware designs, typically on a contract or project basis rather than as full-time employees. They create, implement, and maintain testbenches, sequences, and verification environments to ensure that integrated circuits (ICs) or systems-on-chip (SoCs) meet their design specifications. Their work is crucial for identifying and debugging design flaws before hardware production, reducing costly errors and development cycles. Contract engineers are often hired for specific projects where specialized UVM expertise is needed, allowing organizations to scale their verification teams efficiently.

What are the key skills and qualifications needed to thrive as a Contract UVM Verification Engineer, and why are they important?

To thrive as a Contract UVM Verification Engineer, expertise in digital design verification, SystemVerilog, and Universal Verification Methodology (UVM) is essential, often supported by a degree in electrical or computer engineering. Familiarity with simulation tools like Synopsys VCS, Cadence Incisive, and scripting languages such as Python or Perl is typically required. Strong analytical thinking, attention to detail, and effective communication skills help engineers collaborate and identify complex design issues. These abilities ensure the delivery of robust, error-free hardware designs within project timelines and specifications.
More about Contract Uvm Verification jobs
What cities are hiring for Contract Uvm Verification jobs? Cities with the most Contract Uvm Verification job openings:
What are the most commonly searched types of Uvm Verification jobs? The most popular types of Uvm Verification jobs are:
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Contract Uvm Verification jobs near you
Infographic showing various Contract Uvm Verification job openings in the United States as of May 2026, with employment types broken down into 56% Full Time, 24% Part Time, and 20% Contract. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Senior FPGA Engineer

Senior FPGA Engineer

Amarx Search, Inc.

Cincinnati, OH

$106K - $197K/yr

Other

Posted 4 days ago

Job description

Amarx Search, Inc. - amarx.com

Direct Hire - Full Time position in Cincinnati, OH
Pay: $106,500 to $197,500 based on relevant experience
Position ID: 2730

An excellent position with a large defense technology company delivering innovative mission solutions

* Senior FPGA Engineer *

Please apply ONLY if you have extensive FPGA and Verilog experience

United States Citizenship is required due to government contract requirements

We can ONLY consider your application if you have:
1: Bachelor's Degree
2: 6+ years of relevant experience (4 with Master's, 10 with no degree)
3: Knowledge using Verilog for Logic Design.
4: Programming experience in C for embedded systems, including development of algorithms, manipulation of data structures, and implementing highly optimized code.
5: Experience with lab tools: Logic Analyzers, oscilloscopes, JTAG/ICE debuggers and protocol analyzers.
6: Familiar with hardware, software and firmware development methodologies to ensure quality and time-to-market (design verification, code reviews, unit testing, prototyping and product testing).
7: Familiar working with code version control repository tools, such as Subversion (SVN), GIT or TFS.
8: Digital Design practices and principles, logic design and architecture and experience with HDL's (i.e Verilog, VHDL).

We are looking for an outstanding Hardware Engineer to be responsible for architecture, design and development of next generation Electronic Safe and Arm Devices utilizing the latest state of the art technologies. The ideal candidate for this role would share a passion for creating and innovating new technologies in a highly dynamic, fast-paced environment. We are looking for highly talented, motivated, and versatile engineers that can create the next generation fuzing solutions. ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A interfaces, communication protocols, state machines, timer chains, etc. used in Electronic Safe and Arm Devices (Fuzes) for DOD weapon systems. Microsemi / Actel is our targeted FPGA and QuestaSim is our simulation tool. The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and C# based microcontroller development.

DESIRED (not required) SKILLS:
:: Knowledge using SystemVerilog for verification with AVM, VMM, OVM, or UVM a plus.
:: Developing C# source code targeting enhanced Flash Microcontrollers.
:: Good English knowledge (speech and writing)

Duties and Responsibilities
== Analysis of the requirements, architecture definition, design and debug of FPGA and associated hardware and microcontroller products and associated firmware.
== Developing Verilog HDL targeting Antifuse and enhanced Flash FPGA's.
== Performing effective analysis of functional issues or performance profiling with the hardware and firmware in test environments or target host systems.
== Contribute to process improvements to ensure hardware-firmware quality and time-to-market.

Please send resume to - Amarx Search, Inc. - amarx.com

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About Amarx Search

Sourced by ZipRecruiter

Industry

Recruiting and staffing services

Company size

11 - 50 Employees

Headquarters location

Simi Valley, CA, US

Year founded

1987

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