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Contract Uvm Verification Jobs (NOW HIRING)

Mythic

Senior Design Verification Engineer

Austin, TX

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Senior Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Senior Design Verification Engineer

Austin, TX

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Senior Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Palo Alto, CA

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Mythic

Design Verification Engineer

Austin, TX

$120K - $225K/yr

... contracts across multiple markets. The salary range for this position is $120,000-$225,000 ... Testbench development and execution using UVM or other advanced DV methodologies. * Creation of ...

Etched

Formal Verification - DV

San Jose, CA · On-site

$2.0K/mo

Partner with UVM DV, emulation, software, and firmware teams to align formal verification with ... Vendor IP integration, encrypted or black-box IP verification, VIP configuration, and contract ...

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Contract Uvm Verification information

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$80K

$142.6K

$203.5K

How much do contract uvm verification jobs pay per year?

As of Sep 1, 2026, the average yearly pay for contract uvm verification in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a contract UVM verification engineer?

Contract UVM Verification engineers are professionals who specialize in using the Universal Verification Methodology (UVM) to verify the functionality of digital hardware designs, typically on a contract or project basis rather than as full-time employees. They create, implement, and maintain testbenches, sequences, and verification environments to ensure that integrated circuits (ICs) or systems-on-chip (SoCs) meet their design specifications. Their work is crucial for identifying and debugging design flaws before hardware production, reducing costly errors and development cycles. Contract engineers are often hired for specific projects where specialized UVM expertise is needed, allowing organizations to scale their verification teams efficiently.

What are the key skills and qualifications needed to thrive as a contract UVM verification engineer, and why are they important?

To thrive as a Contract UVM Verification Engineer, expertise in digital design verification, SystemVerilog, and Universal Verification Methodology (UVM) is essential, often supported by a degree in electrical or computer engineering. Familiarity with simulation tools like Synopsys VCS, Cadence Incisive, and scripting languages such as Python or Perl is typically required. Strong analytical thinking, attention to detail, and effective communication skills help engineers collaborate and identify complex design issues. These abilities ensure the delivery of robust, error-free hardware designs within project timelines and specifications.

What are some common challenges faced by contract UVM verification engineers when joining new projects, and how can they be addressed?

Contract UVM Verification engineers often face challenges such as quickly ramping up on unfamiliar codebases, understanding project-specific verification methodologies, and integrating with established teams. To overcome these, it’s important to proactively communicate with team members, thoroughly review project documentation, and leverage reusable UVM components where possible. Establishing strong lines of communication and participating in regular sync meetings can help bridge knowledge gaps and ensure alignment with project goals.

What is the difference between Contract Uvm Verification vs Contract SystemVerilog Verification?

AspectContract Uvm VerificationContract SystemVerilog Verification
CredentialsUVM Certification, Verilog/SystemVerilog knowledgeVerilog/SystemVerilog expertise, verification certifications
Work EnvironmentASIC/FPGA verification teams, EDA toolsASIC/FPGA verification teams, EDA tools
Industry UsageCommon in UVM-based verification environmentsUsed broadly in SystemVerilog verification projects
Comparison FocusUVM methodology specificsSystemVerilog language features

Contract Uvm Verification primarily focuses on UVM methodology and testbench development, while Contract SystemVerilog Verification emphasizes proficiency in SystemVerilog language features for verification tasks. Both roles often overlap but differ in their core focus areas within the verification process.

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Contract Uvm Verification jobs near you
Infographic showing various Contract Uvm Verification job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 80% Full Time, 15% Part Time, 3% Contract, and 1% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Senior FPGA Engineer (DOD cleared) with Security Clearance

VertuCom

Tucson, AZ • On-site

$111K - $143K/yr

Other

Re-posted 16 days ago

Job description


Senior FPGA Engineer Location: Tucson, AZ Schedule: On-Site Clearance: Secret clearance or higher required prior to start Role Summary Seeking a senior-level FPGA Engineer to support the design, development, verification, and integration of production-quality FPGA solutions for advanced defense systems. This role covers the full FPGA lifecycle from requirements and architecture through VHDL coding, simulation, place-and-route, integration, debug, and production release support. Key Responsibilities * Develop and verify FPGA designs using VHDL. * Support FPGA architectures for system-level applications. * Translate system-level requirements into FPGA requirements. * Perform simulation, synthesis, place-and-route, timing closure, integration, and debug. * Work with circuit card designers and systems engineers to define interfaces and design requirements. * Support FPGA designs involving RF/EO DSP, controls, data links, embedded processing, processor interfaces, and gigabit serial interfaces. * Create technical documentation, including requirements, verification plans, and user guides. * Support internal and external technical reviews as needed. Required Skills * 8+ years of FPGA engineering experience. * VHDL coding and digital design experience. * Experience with Xilinx, Altera, or Microsemi FPGA devices and tool flows. * Hands-on FPGA integration and debug experience. * Experience delivering FPGA solutions into system-level applications. * Ability to support FPGA work from requirements definition through integration and test. * Secret clearance or higher required prior to start. Preferred Skills * Radar or image processing experience. * Embedded systems experience using ARM, MicroBlaze, or Nios processors. * Experience with gigabit serial interfaces or multi-gigabit transceivers. * SystemVerilog / UVM verification experience. * Experience with emulation platforms such as Veloce. * Strong technical documentation and review support experience.

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