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Remote Asic Rtl Design Engineer Jobs (NOW HIRING)

K2 Space

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

Aalyria

Lead RTL/FPGA Design Engineer

$170K - $195K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

This is a remote position that will include occasional travel to our Mountain View office location ... Familiarity with high-speed ASIC/FPGA synthesis, place and route (P&R), and static timing analysis ...

Meta

ASIC Engineer, Power

Austin, TX · On-site +1

$146K/yr

As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Cornelis Networks

PCIe ASIC Design Engineer

San Jose, CA · On-site +1

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... remote roles. Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and ... Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ...

Cornelis Networks, Inc.

PCIe ASIC Design Engineer

San Jose, CA · Remote

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... remote roles. Cornelis Networks is hiring a Senior ASIC Design Engineer to lead the design and ... Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

Navtech, Inc.

Digital Design Engineer.

$139K/yr

REMOTE Duration : 6+ Months on W2 Visa : Independent candidates who are eligible to work for any ... Role responsibilities (including, but not limited to): • Own an ASIC IP RTL implementation for IP ...

Sapsol Technologies Inc

Lead ASIC DFT Engineer

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ... Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and ...

Sapsol Technologies Inc

Asics Engineer

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Strong hands-on experience in ASIC DFT with end-to-end ownership. * Solid understanding of DFT ...

Positron AI

Mid-End ASIC Engineer, Principal

$190K - $280K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and ... Remote-first culture with a company-provided computer and home office setup Compensation and future

K2 Space

Senior ASIC Emulation Engineer

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...

MatX

ASIC/SOC Silicon Physical Design Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... RTL to GDSII * Own entire subsystems or subsets and/or chip-level Physical Design deliverables ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

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Remote Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do remote asic rtl design engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for remote asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a remote ASIC RTL design engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a remote ASIC RTL design engineer?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What are some common challenges faced by remote ASIC RTL design engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

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Remote Asic Rtl Design Engineer jobs near you
Infographic showing various Remote Asic Rtl Design Engineer job openings in the United States as of August 2026, with employment types broken down into 67% Full Time, and 33% Contract. Highlights an 100% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Principal ASIC Physical Design Engineer

K2 Space

OR • On-site, Remote

$190K - $280K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 24 days ago

Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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