ZipRecruiter

Log In

2

Remote Asic Rtl Design Engineer Jobs (NOW HIRING)

Meta

ASIC Engineer, Power

Sunnyvale, CA · On-site +1

$146K/yr

As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Aalyria

Lead RTL/FPGA Design Engineer

$170K - $195K/yr

This is a remote position that will include occasional travel to our Mountain View office location ... Familiarity with high-speed ASIC/FPGA synthesis, place and route (P&R), and static timing analysis ...

K2 Space

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

Meta

ASIC Engineer, Power

Austin, TX · On-site +1

$146K/yr

As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Cornelis Networks

PCIe ASIC Design Engineer

San Jose, CA · On-site +1

... remote roles. Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and ... Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

... remote roles. Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and ... Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

Navtech, Inc.

Digital Design Engineer.

$139K/yr

REMOTE Duration : 6+ Months on W2 Visa : Independent candidates who are eligible to work for any ... Role responsibilities (including, but not limited to): • Own an ASIC IP RTL implementation for IP ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

Sapsol Technologies Inc

Lead ASIC DFT Engineer

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ... Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and ...

Sapsol Technologies Inc

Asics Engineer

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Strong hands-on experience in ASIC DFT with end-to-end ownership. * Solid understanding of DFT ...

Positron AI

Mid-End ASIC Engineer, Principal

$190K - $280K/yr

Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and ... Remote-first culture with a company-provided computer and home office setup Compensation and future

K2 Space

Senior ASIC Emulation Engineer

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

Tensordyne

Sr. Staff ASIC Design Engineer

Sunnyvale, CA · On-site +1

Architect and implement complex RTL designs. * Scope third party IP requirements and solicit ... Required Qualifications: * 10+ years of ASIC design experience with a demonstrable track record of ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...

previous pagenext page

Showing results 21-40

All JobsRemote JobsTechnology JobsDesktop Support JobsDesktop Engineer JobsRemote Asic Rtl Design Engineer Jobs

Remote Asic Rtl Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do remote asic rtl design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for remote asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a remote ASIC RTL design engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a remote ASIC RTL design engineer?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What are some common challenges faced by remote ASIC RTL design engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

More about Remote Asic Rtl Design Engineer jobs

What cities are hiring for Remote Asic Rtl Design Engineer jobs?

Cities with the most Remote Asic Rtl Design Engineer job openings:

What are the most commonly searched types of Asic Rtl Design Engineer jobs?

The most popular types of Asic Rtl Design Engineer jobs are:

What states have the most Remote Asic Rtl Design Engineer jobs?

States with the most job openings for Remote Asic Rtl Design Engineer jobs include:

What are popular job titles related to Remote Asic Rtl Design Engineer jobs?

For Remote Asic Rtl Design Engineer jobs, the most frequently searched job titles are:

Remote Asic Rtl Design Engineer jobs near you
Infographic showing various Remote Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ASIC Engineer, Power

Sunnyvale, CA • On-site, Remote

Meta
Internet and IT • 10K+ employees
Learn more about Metaexternal

$146K/yr

Full-time

Re-posted 14 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

139th of 247 rated software companies

Job description

Meta is building custom silicon to power the infrastructure that underlies its family of products and services. As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and maintain power analysis and optimization flows that enable silicon engineers across the organization to accurately model, estimate, and reduce power consumption in custom ASIC designs. In this role, you will work at the intersection of EDA tooling, physical design, and power methodology, helping to define the infrastructure that shapes how Meta's next-generation chips are designed and verified.
ASIC Engineer, Power Responsibilities:
  • Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools
  • Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow
  • Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs
  • Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround time
  • Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments and recommendations
  • Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages
  • Establish power budgets and track power metrics across design milestones, communicating results and risks to cross-functional stakeholders
  • Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs and identifying systemic opportunities
  • Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques
  • Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Minimum Qualifications:
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience in ASIC design or physical design with a focus on power analysis, power optimization, or power signoff
  • Experience developing or maintaining EDA flows for power analysis using tools such as Synopsys PrimePower, Cadence Voltus, or equivalent
  • Experience with power intent specification languages such as UPF or CPF and their application across RTL-to-GDSII flows
  • Experience scripting in Python, Tcl, or shell to build and automate EDA infrastructure workflows
  • Experience collaborating across RTL design, physical design, and verification disciplines to drive power closure on complex ASIC designs

Preferred Qualifications:
  • Experience evaluating and qualifying new EDA tools or methodologies in a production silicon environment
  • Familiarity with custom or semi-custom design flows for high-performance computing or data center silicon
  • Experience with low-power design techniques including clock gating, power gating, multi-voltage domain design, and dynamic voltage and frequency scaling
  • Background in developing internal EDA infrastructure tooling or flow automation at scale across multiple concurrent design projects

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$146,000/year to $209,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

What Meta employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply