ZipRecruiter

Log In

2

Remote Asic Rtl Design Engineer Jobs (NOW HIRING)

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

... remote roles. Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and ... Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

Navtech, Inc.

Digital Design Engineer.

$139K/yr

REMOTE Duration : 6+ Months on W2 Visa : Independent candidates who are eligible to work for any ... Role responsibilities (including, but not limited to): • Own an ASIC IP RTL implementation for IP ...

K2 Space

ASIC Design Verification Engineer

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the ... Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI)

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Quest Global

Microarchitecture Lead / RTL

Santa Clara, CA · Remote

$160K - $240K/yr

... in ASIC/SoC micro-architecture and RTL design * Strong expertise in Verilog/SystemVerilog ... end engineering solutions by leveraging our deep industry knowledge and digital expertise. By ...

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...

Lockheed Martin

ASIC & FPGA Design Engineer Stf

Orlando, FL · On-site +1

$114K - $158K/yr

You will be the ASIC & FPGA Design Engineer for the ASIC/FPGA department at Lockheed Martin ... This position is remote. MUST BE A U.S. CITIZEN - This position is located at a facility that ...

next page

Showing results 1-20

All JobsRemote Asic Rtl Design Engineer Jobs

Remote Asic Rtl Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do remote asic rtl design engineer jobs pay per year?

As of Jun 20, 2026, the average yearly pay for remote asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the salary of ASIC design engineer?

The salary of an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in RTL design and verification can earn higher compensation, often exceeding $180,000.

What is a Remote ASIC RTL Design Engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What is the salary of RTL design engineer?

The salary of an RTL design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages like VHDL or Verilog can earn higher compensation.

What are the key skills and qualifications needed to thrive as a Remote ASIC RTL Design Engineer, and why are they important?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What engineers make $500,000?

Senior ASIC RTL Design Engineers with extensive experience, specialized skills in hardware description languages like Verilog or VHDL, and a strong understanding of chip architecture can reach or exceed $500,000 in total compensation, especially in high-cost-of-living regions or at top-tier companies. Achieving this level often requires advanced certifications, leadership roles, and a track record of successful project delivery.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

What are some common challenges faced by Remote ASIC RTL Design Engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.

Are ASIC design engineers in demand?

ASIC design engineers are in high demand due to the growing need for custom integrated circuits in industries like consumer electronics, automotive, and data centers. Skills in RTL design, verification, and hardware description languages such as VHDL or Verilog are highly valued, and employment opportunities are expected to remain strong as technology advances.
More about Remote Asic Rtl Design Engineer jobs
What cities are hiring for Remote Asic Rtl Design Engineer jobs? Cities with the most Remote Asic Rtl Design Engineer job openings:
What are the most commonly searched types of Asic Rtl Design Engineer jobs? The most popular types of Asic Rtl Design Engineer jobs are:
What states have the most Remote Asic Rtl Design Engineer jobs? States with the most job openings for Remote Asic Rtl Design Engineer jobs include:
What job categories do people searching Remote Asic Rtl Design Engineer jobs look for? The top searched job categories for Remote Asic Rtl Design Engineer jobs are:
Remote Asic Rtl Design Engineer jobs near you
Infographic showing various Remote Asic Rtl Design Engineer job openings in the United States as of June 2026, with employment types broken down into 75% Full Time, 5% Part Time, and 20% Contract. Highlights an 100% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
PCIe ASIC Design Engineer

PCIe ASIC Design Engineer

Cornelis Networks

Austin, TX • On-site, Remote

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 5 days ago

Job description

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.


Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6), integration into high performance ASICs, emulation and post silicon bring-up.


Key Responsibilities:

  • Own end-to-end integration of PCIe IP into complex ASIC designs.
  • Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
  • Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
  • Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
  • Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
  • Debug functional and performance issues at RTL, gate-level, and silicon.
  • Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
  • Provide mentorship to junior engineers and help define PCIe subsystem development best practices.
  • Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms


Minimum Qualifications:

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
  • Proven experience in silicon bring-up and debug of high-speed interfaces.
  • Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
  • Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
  • Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
  • Strong scripting (Python, Perl, TCL) and debugging skills.
  • Strong verbal and written communication skills.


Preferred Qualifications:

  • Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
  • Exposure to CXL, CCIX, or other cache-coherent interconnects.
  • Background in data center or AI/ML accelerator architectures.
  • Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation.


Location: This is a remote position for employees residing within the United States.


We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Apply