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Vice President Design Verification Engineer Jobs in California

Mythic

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Mythic

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Insilico

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Nutanix

GSoC Design Verification Engineer

San Diego, CA · On-site

$99 - $148/hr

As part of the Global SoC organization, our ASIC Design Verification Engineers bring deep expertise in CPUs, memory systems , High Bandwidth Compute (HBC), AI inference acceleration, and ASIC design ...

General Atomics

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

GA-EMS has an exciting opportunity located in Rancho Bernardo, CA for a Design Verification Engineer to join the Design Services Team. Under general supervision with limited review, this position is ...

Qualcomm

GSoC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

As part of the Global SoC organization, our ASIC Design Verification Engineers bring deep expertise in CPUs, memory systems, High Bandwidth Compute (HBC), AI inference acceleration, and ASIC design ...

Insilico

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

We are seeking highly motivated and experienced Design Verification Engineers to join our Data Center SoC Verification team. In this role, you will be responsible for verifying next-generation Data ...

On Board Experiential

VP of Design

Los Angeles, CA · On-site

SUMMARY OF POSITION The Vice President, Design is a senior creative leader responsible for ... Work with CCO and Creative Leadership to drive and develop department programming, including ...

Broadcom

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer ...

Epitec

Design Verification Engineer III

Sunnyvale, CA · On-site

$159K - $194K/yr

Design Verification Engineer III Contract Duration: 6 months, possible extension Location: Sunnyvale, CA Work Arrangement: Hybrid (3 days onsite) Summary Design Verification Engineer for wearables ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

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Vice President Design Verification Engineer information

What does a vice president design verification engineer do?

A Vice President Design Verification Engineer is a senior executive responsible for overseeing the verification of electronic design projects, ensuring that hardware and integrated circuits meet all functional and quality requirements before production. They lead teams of engineers, set verification strategies, and manage processes to identify and fix design flaws early in the development cycle. Additionally, they collaborate with other executive leaders to align verification goals with overall business objectives and technological advancements. Their role is critical in ensuring the reliability, performance, and compliance of complex electronic systems.

What are the key skills and qualifications needed to thrive as a vice president design verification engineer?

To thrive as a Vice President Design Verification Engineer, you need extensive experience in hardware design verification, a strong background in electrical engineering or a related field, and leadership capabilities, often supported by an advanced degree. Proficiency with verification methodologies such as UVM, SystemVerilog, formal verification tools, and project management systems is typically required. Exceptional communication, strategic thinking, and team leadership are critical soft skills that set outstanding candidates apart. These skills and qualities ensure rigorous product validation, efficient team performance, and successful delivery of complex semiconductor projects.

What are the main challenges a vice president design verification engineer faces when leading large verification teams across multiple projects?

One of the main challenges in this role is ensuring alignment and consistency in verification methodologies across diverse project teams, often distributed globally. Balancing resource allocation, maintaining high-quality standards, and managing tight project timelines are also significant responsibilities. Additionally, fostering effective collaboration between design, verification, and software teams is essential to quickly resolve issues and achieve project milestones. Strong leadership and communication skills are crucial for driving innovation while maintaining operational excellence.

What is the difference between Vice President Design Verification Engineer vs Senior Design Verification Engineer?

AspectVice President Design Verification EngineerSenior Design Verification Engineer
CredentialsTypically requires a master's or PhD in Electrical Engineering or Computer Science, with extensive industry experienceBachelor's or master's degree in related field, with several years of verification experience
Work EnvironmentExecutive leadership, strategic planning, cross-department collaborationHands-on verification tasks, test plan development, simulation and debugging
Industry UsageUsed in large tech and semiconductor companies at an executive levelCommon in semiconductor, electronics, and hardware design companies

The Vice President Design Verification Engineer focuses on strategic oversight and leadership at an executive level, while the Senior Design Verification Engineer handles detailed verification tasks and technical execution. Both roles require strong technical backgrounds, but differ in scope and responsibilities.

What are the most commonly searched types of Design Verification Engineer jobs in California?

The most popular types of Design Verification Engineer jobs in California are:

What are popular job titles related to Vice President Design Verification Engineer jobs in California?

For Vice President Design Verification Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Vice President Design Verification Engineer jobs in California look for?

The top searched job categories for Vice President Design Verification Engineer jobs in California are:

What cities in California are hiring for Vice President Design Verification Engineer jobs?

Cities in California with the most Vice President Design Verification Engineer job openings:

Vice President Design Verification Engineer jobs near you
Infographic showing various Vice President Design Verification Engineer job openings in California as of August 2026, with employment types broken down into 83% Full Time, 12% Part Time, and 5% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution.

Design Verification Engineer

Mythic

Palo Alto, CA • On-site

$120K - $225K/yr

Full-time

Re-posted 16 days ago

Job description

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life.

About Us:
Mythic is building the future of AI computing with breakthrough analog technology that delivers 100 the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 C to +125 C, making it ideal for industrial, automotive, aerospace, and defense.

We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.

The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location.

Design Verification at Mythic:
At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our custom dataflow architecture that is the backbone of our chip design. DV engineers collaborate with many teams, including RTL design, architecture modeling, custom analog IP, compiler, emulation and post-silicon to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.
Responsibilities
  • Hands on system-level and block-level verification.
  • Development of test plans and coverage plans.
  • Testbench development and execution using UVM or other advanced DV methodologies.
  • Creation of verification infrastructure and flows.
  • Leverage architecture models and emulation environments to help verify large AI network functionality on the design.
  • Further responsibilities will depend on background and skills.
Requirements
  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 3+ years of industry experience developing verification testbenches.
  • Knowledge of verification methodologies.
  • Knowledge of computer architecture.
  • Understanding of Verilog, SystemVerilog, and UVM.
  • Proven track record of first-pass silicon success.
  • Strong communication skills, both written and spoken.
At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.
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