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Remote Physical Verification Engineer Jobs (NOW HIRING)

FortifyIQ

Verification Engineer (Remote)

Salem, MA · Remote

$148.60K/yr

We're seeking a Verification Engineer to contribute to the validation of advanced chip designs. You'll help create and maintain UVM environments, write tests, and ensure functional coverage for high ...

Futran Tech Solutions Pvt. Ltd.

Physical Design Engineer

$139.20K - $143.30K/yr

Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance ... Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub ...

MatX

Formal Verification Engineer

Mountain View, CA · On-site +1

$140K - $420K/yr

Remote Perks - We work remotely Monday & Friday, supported by home-tech setup and remote wifi ... physical or mental disability, medical condition, marital/domestic partner status, military and ...

Mercor

Design Verification Engineer

San Jose, CA · Remote

$100 - $175/hr

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Design and verify RTL components using Verilog/SystemVerilog . * Collaborate with architecture ...

New

FortifyIQ

Senior Verification Engineer (Remote)

Salem, MA · Remote

$114.20K - $156.80K/yr

We're looking for a Senior Verification Engineer to play a key role in verifying complex SoC and subsystem designs. You'll work hands-on with design and architecture teams to ensure functionality ...

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$80K

$142.6K

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How much do remote physical verification engineer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for remote physical verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Remote Physical Verification Engineer, and why are they important?

To thrive as a Remote Physical Verification Engineer, you need a strong background in electrical engineering, solid understanding of VLSI design, and hands-on experience with semiconductor physical verification processes. Expertise in using EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with DRC/LVS checks and scripting languages such as Python or TCL, are typically required. Exceptional problem-solving, attention to detail, and effective remote communication skills help you collaborate efficiently with distributed teams. These skills and qualities are crucial to ensuring chip designs meet all physical and manufacturing requirements, minimizing costly errors and delays.

How does a Remote Physical Verification Engineer typically collaborate with design and layout teams to resolve verification issues?

As a Remote Physical Verification Engineer, collaboration with design and layout teams is essential for resolving verification issues efficiently. Communication is often handled through video meetings, project management tools, and shared documentation platforms. You'll review error reports, discuss potential fixes, and provide guidance on design rule checks (DRC) and layout versus schematic (LVS) violations. Being proactive in documenting findings and maintaining clear channels with both on-site and remote colleagues helps ensure quick turnaround and high-quality tapeouts.

What is a Remote Physical Verification Engineer?

A Remote Physical Verification Engineer is a professional who specializes in checking the physical layout of integrated circuits (ICs) to ensure they meet design and manufacturing specifications. Working remotely, these engineers use specialized electronic design automation (EDA) tools to verify aspects such as design rule checks (DRC) and layout versus schematic (LVS) compliance. They collaborate with design teams to identify and resolve potential issues before fabrication, helping to prevent costly errors and delays. This role requires strong knowledge of semiconductor design, EDA software, and remote collaboration skills.

What is the difference between Remote Physical Verification Engineer vs Physical Verification Engineer?

AspectRemote Physical Verification EngineerPhysical Verification Engineer
CredentialsTypically requires VLSI design, verification certifications, and familiarity with EDA toolsSimilar credentials, often with additional emphasis on physical design tools
Work EnvironmentPrimarily remote, collaborating via online toolsUsually onsite or hybrid, depending on company policy
Industry UsageUsed in semiconductor and chip design companies, especially in remote teamsCommon in semiconductor industry, both onsite and remote roles
Search & Comparison IntentOften searched by candidates looking for remote roles in physical verificationMore general, includes onsite roles

The Remote Physical Verification Engineer and Physical Verification Engineer roles share similar credentials and industry usage. The key difference lies in the work environment, with the remote role allowing work from anywhere, while the onsite role may require physical presence. Both positions are vital in semiconductor design, with remote options increasing flexibility for professionals in the field.

More about Remote Physical Verification Engineer jobs
What cities are hiring for Remote Physical Verification Engineer jobs? Cities with the most Remote Physical Verification Engineer job openings:
What are the most commonly searched types of Physical Verification Engineer jobs? The most popular types of Physical Verification Engineer jobs are:
What states have the most Remote Physical Verification Engineer jobs? States with the most job openings for Remote Physical Verification Engineer jobs include:
What job categories do people searching Remote Physical Verification Engineer jobs look for? The top searched job categories for Remote Physical Verification Engineer jobs are:
Remote Physical Verification Engineer jobs near you
Infographic showing various Remote Physical Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 5% As Needed, 92% Full Time, 2% Part Time, and 1% Contract. Highlights an 33% Physical, 3% Hybrid, and 64% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Design Verification Engineer - Remote

Futran Tech Solutions Pvt. Ltd.

Remote

$139.20K - $169.90K/yr

Full-time

Posted 18 days ago

Job description

Role - Design Verification Engineer
Location: Remote (must be aligned with PST time zone / willing to work PST hours)
Contract Term: Contract
Job Description:
We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build System Verilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write System Verilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.

Qualifications
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (e.g. Python, Perl, TCL) and revision control system (e.g. Git).

Nice to Have
  • Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
  • Familiarity with developing and integrating reference models.
  • Understanding of RTL design flows and some industry standard interfaces (e.g. APB/AHB/AXI).
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus.

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