ZipRecruiter

Log In

2

Remote Physical Verification Engineer Jobs in California

MatX

Formal Verification Engineer

Mountain View, CA · On-site +1

$150K - $287K/yr

Remote Perks - We work remotely Monday & Friday, supported by home-tech setup and remote wifi ... physical or mental disability, medical condition, marital/domestic partner status, military and ...

MatX

Design Verification Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ... physical or mental disability, medical condition, marital/domestic partner status, military and ...

MatX

SoC Design Verification Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ... physical or mental disability, medical condition, marital/domestic partner status, military and ...

next page

Showing results 1-20

All JobsPhysical Verification Engineer JobsRemote Physical Verification Engineer JobsRemote Physical Verification Engineer Jobs in California

Remote Physical Verification Engineer information

How does a Remote Physical Verification Engineer typically collaborate with design and layout teams to resolve verification issues?

As a Remote Physical Verification Engineer, collaboration with design and layout teams is essential for resolving verification issues efficiently. Communication is often handled through video meetings, project management tools, and shared documentation platforms. You'll review error reports, discuss potential fixes, and provide guidance on design rule checks (DRC) and layout versus schematic (LVS) violations. Being proactive in documenting findings and maintaining clear channels with both on-site and remote colleagues helps ensure quick turnaround and high-quality tapeouts.

What is a Remote Physical Verification Engineer?

A Remote Physical Verification Engineer is a professional who specializes in checking the physical layout of integrated circuits (ICs) to ensure they meet design and manufacturing specifications. Working remotely, these engineers use specialized electronic design automation (EDA) tools to verify aspects such as design rule checks (DRC) and layout versus schematic (LVS) compliance. They collaborate with design teams to identify and resolve potential issues before fabrication, helping to prevent costly errors and delays. This role requires strong knowledge of semiconductor design, EDA software, and remote collaboration skills.

What are the key skills and qualifications needed to thrive as a Remote Physical Verification Engineer, and why are they important?

To thrive as a Remote Physical Verification Engineer, you need a strong background in electrical engineering, solid understanding of VLSI design, and hands-on experience with semiconductor physical verification processes. Expertise in using EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with DRC/LVS checks and scripting languages such as Python or TCL, are typically required. Exceptional problem-solving, attention to detail, and effective remote communication skills help you collaborate efficiently with distributed teams. These skills and qualities are crucial to ensuring chip designs meet all physical and manufacturing requirements, minimizing costly errors and delays.

What is the difference between Remote Physical Verification Engineer vs Physical Verification Engineer?

AspectRemote Physical Verification EngineerPhysical Verification Engineer
CredentialsTypically requires VLSI design, verification certifications, and familiarity with EDA toolsSimilar credentials, often with additional emphasis on physical design tools
Work EnvironmentPrimarily remote, collaborating via online toolsUsually onsite or hybrid, depending on company policy
Industry UsageUsed in semiconductor and chip design companies, especially in remote teamsCommon in semiconductor industry, both onsite and remote roles
Search & Comparison IntentOften searched by candidates looking for remote roles in physical verificationMore general, includes onsite roles

The Remote Physical Verification Engineer and Physical Verification Engineer roles share similar credentials and industry usage. The key difference lies in the work environment, with the remote role allowing work from anywhere, while the onsite role may require physical presence. Both positions are vital in semiconductor design, with remote options increasing flexibility for professionals in the field.

What are popular job titles related to Remote Physical Verification Engineer jobs in California? For Remote Physical Verification Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Remote Physical Verification Engineer jobs in California look for? The top searched job categories for Remote Physical Verification Engineer jobs in California are:
What cities in California are hiring for Remote Physical Verification Engineer jobs? Cities in California with the most Remote Physical Verification Engineer job openings:
Remote Physical Verification Engineer jobs near you

Physical Verification Engineer

Celero Communications, Inc.

San Jose, CA • On-site, Remote

$150K - $250K/yr

Full-time

Posted 2 days ago

New

Job description

Senior to Principal Full-Chip Physical Verification Engineer roles
Locations: San Jose, CA (preferred) or Irvine, CA (HQ) or remote
Key Responsibilities
Team & Project Leadership
• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks
Physical Verification Ownership
• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules
Cross-Functional Collaboration
• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews
Required Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications
Proven hands-on experience with:
• Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV
Strong expertise in:
• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration
Preferred Qualifications
• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)