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Internship Physical Verification Engineer Jobs (NOW HIRING)

Intel

Physical Verification Engineer

Hillsboro, OR

$148K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... experience, internship experience and / or schoolwork/classes/research. The preferred ...

Intel

Physical Verification Engineer

Santa Clara, CA · On-site

$159K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... experience, internship experience and / or schoolwork/classes/research. The preferred ...

Intel

Physical Verification Engineer

Phoenix, AZ

$135K/yr

... Physical Verification Application Engineer provides specialized technical support to Intel Foundry ... experience, internship experience and / or schoolwork/classes/research. The preferred ...

Apple

GPU Physical Verification Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Description As a GPU Physical Verification engineer, you will work closely with the Physical Design team to drive physical verification aspects in the design cycle. You will work with physical design ...

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Internship Physical Verification Engineer information

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How much do internship physical verification engineer jobs pay per hour?

As of Jul 21, 2026, the average hourly pay for internship physical verification engineer in the United States is $19.31, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $20.91 per hour, depending on experience, location, and employer.

What is the difference between Internship Physical Verification Engineer vs Internship Digital Verification Engineer?

AspectInternship Physical Verification EngineerInternship Digital Verification Engineer
Primary FocusVerifying physical chip layouts and manufacturing readinessVerifying digital circuit functionality and logic design
Required SkillsHardware design, physical design tools, layout verificationHardware description languages, simulation, testbench development
Work EnvironmentSemiconductor fabrication and physical design teamsASIC/FPGA design teams, digital logic development
Industry UsageVLSI, semiconductor manufacturingASIC, FPGA, digital IC design

Both roles are internship positions in the semiconductor industry, focusing on different aspects of chip design. The Physical Verification Engineer internship emphasizes physical layout and manufacturing checks, while the Digital Verification Engineer internship centers on verifying digital logic functionality. Candidates should have relevant technical skills in their respective areas, and both roles offer valuable experience in the semiconductor design process.

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Internship Physical Verification Engineer jobs near you
Infographic showing various Internship Physical Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $40,174 per year, or $19.3 per hour.
Physical Verification Engineer

Physical Verification Engineer

Intel

Hillsboro, OR

$148K/yr

Full-time

Medical, Retirement, PTO

Re-posted yesterday

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

11th of 143 rated electronics manufacturers

Job description

Job Details:Job Description: 

About Intel Foundry Services

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview

The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.

Key Responsibilities

Physical Verification Support & Issue Resolution

  • Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges

  • Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution

  • Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

Technical Content Development & Training

  • Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams

  • Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs

  • Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

Verification Methodology Leadership

  • Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)

  • Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations

  • Drive methodology improvements to streamline customer design workflows and enhance verification productivity

Customer Engagement & Technical Excellence

  • Deliver customer-facing technical support with focus on physical verification challenges and solutions

  • Support customers through complex verification issues and advanced process technology adoption

  • Ensure maximum customer satisfaction through expert guidance and responsive technical support

Core Competencies

  • Self-driven and results-oriented with capability to effectively manage multiple complex tasks

  • Strong analytical problem-solving skills for complex physical verification challenges

  • Effective communication skills with experience in collaboration, active listening, and providing constructive feedback

Qualifications:

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

  • US Citizenship required

  • Ability to obtain a US Government Security Clearance

  • Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study

  • 3+ years of experience with advanced CMOS processes (22nm and below)

  • 3+ years of combined experience in layout verification and parasitic extraction EDA tools

  • 3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)

Preferred Qualifications

  • Active US Government Security Clearance with a minimum of Secret level

  • Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study

  • Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)

  • Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools

  • Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools

  • Rule deck coding experience in ICV, Calibre or Pegasus EDA tools

  • Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work

  • Customer facing experience

What We Offer

  • Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications

  • Direct customer engagement and technical leadership in advanced semiconductor verification

  • Access to Intel's most advanced foundry technologies and comprehensive verification tool suites

  • Competitive compensation

  • Professional development in physical verification methodologies and foundry services

  • Direct impact on national security through advanced semiconductor verification solutions

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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