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Internship Physical Verification Engineer Jobs in Virginia

Fractile

Physical Design Engineer

Bristol, VA · On-site

$80 - $120/hr

You will collaborate with cross‑functional teams, including logic design, verification, and ... internships. * Familiarity with EDA tools for place & route, STA, and sign‑off. * Basic ...

Fractile

Lead Physical Design Engineer

Bristol, VA · On-site

$120 - $180/hr

As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of ... You will collaborate with cross-functional teams, including logic design, verification, and process ...

GDIT

GDIT 2027 Summer AI / ML Internship

Falls Church, VA · Hybrid

$22.95 - $31.05/hr

... , or other STEM field from a United States-based college or university. * Basic understanding of ... Our Identify Verification Process: As part of the hiring process, we will ask you to complete an ...

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Internship Physical Verification Engineer information

What is the difference between Internship Physical Verification Engineer vs Internship Digital Verification Engineer?

AspectInternship Physical Verification EngineerInternship Digital Verification Engineer
Primary FocusVerifying physical chip layouts and manufacturing readinessVerifying digital circuit functionality and logic design
Required SkillsHardware design, physical design tools, layout verificationHardware description languages, simulation, testbench development
Work EnvironmentSemiconductor fabrication and physical design teamsASIC/FPGA design teams, digital logic development
Industry UsageVLSI, semiconductor manufacturingASIC, FPGA, digital IC design

Both roles are internship positions in the semiconductor industry, focusing on different aspects of chip design. The Physical Verification Engineer internship emphasizes physical layout and manufacturing checks, while the Digital Verification Engineer internship centers on verifying digital logic functionality. Candidates should have relevant technical skills in their respective areas, and both roles offer valuable experience in the semiconductor design process.

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Internship Physical Verification Engineer jobs near you
Infographic showing various Internship Physical Verification Engineer job openings in Virginia as of June 2026, with employment types broken down into 47% Full Time, 49% Part Time, and 4% Contract. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution.

Physical Design Engineer

Fractile

Bristol, VA • On-site

$80 - $120/hr

Other

Posted 5 days ago

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next‑generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign‑off. You will collaborate with cross‑functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:
  • Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign‑off.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
  • Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design‑for‑test (DFT) structures into the physical implementation.
  • Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Work closely with RTL and architecture teams to support design feasibility, constraints, and physical‑aware RTL design.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
  • Familiarity with EDA tools for place & route, STA, and sign‑off.
  • Basic understanding of CMOS technology, semiconductor physics, and process limitations.
  • Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
  • Excellent problem‑solving skills, communication, and teamwork in a collaborative design environment.
  • Interest in working with advanced AI tools and models as part of the design workflow.
  • Experience or coursework in high‑performance computing (HPC), AI accelerators, or networking chips is a plus.
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