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Internship Physical Verification Engineer Jobs (NOW HIRING)

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC ...

Apple

SoC Physical Design Verification Engineer

Beaverton, OR · On-site

$141K - $145K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and ...

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Internship Physical Verification Engineer information

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How much do internship physical verification engineer jobs pay per hour?

As of Jul 22, 2026, the average hourly pay for internship physical verification engineer in the United States is $19.31, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $20.91 per hour, depending on experience, location, and employer.

What is the difference between Internship Physical Verification Engineer vs Internship Digital Verification Engineer?

AspectInternship Physical Verification EngineerInternship Digital Verification Engineer
Primary FocusVerifying physical chip layouts and manufacturing readinessVerifying digital circuit functionality and logic design
Required SkillsHardware design, physical design tools, layout verificationHardware description languages, simulation, testbench development
Work EnvironmentSemiconductor fabrication and physical design teamsASIC/FPGA design teams, digital logic development
Industry UsageVLSI, semiconductor manufacturingASIC, FPGA, digital IC design

Both roles are internship positions in the semiconductor industry, focusing on different aspects of chip design. The Physical Verification Engineer internship emphasizes physical layout and manufacturing checks, while the Digital Verification Engineer internship centers on verifying digital logic functionality. Candidates should have relevant technical skills in their respective areas, and both roles offer valuable experience in the semiconductor design process.

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What cities are hiring for Internship Physical Verification Engineer jobs? Cities with the most Internship Physical Verification Engineer job openings:
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Internship Physical Verification Engineer jobs near you
Infographic showing various Internship Physical Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $40,174 per year, or $19.3 per hour.

Full-Chip Physical Design Verification Engineer

Tenstorrent

Austin, TX • On-site

$100K - $500K/yr

Full-time

Posted 21 days ago

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You'll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we'd love to hear from you.
This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
  • A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
  • A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
  • A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
  • A mentor and technical leader passionate about building efficient, manufacturable silicon.

What We Need
  • BS/MS in Electrical/Electronics Engineering (or related) with 7-14 years of hands-on CPU/IP/SoC physical verification experience.
  • Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
  • Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
  • Scripting proficiency in Python and TCL for automation and flow optimization.

What You Will Learn
  • Advanced physical verification methodologies and flow optimization for next-generation SoCs.
  • Integration and verification strategies for full-chip signoff across advanced process technologies.
  • Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
  • Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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