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Internship Physical Verification Engineer Jobs in Texas

Apple

GPU Physical Verification Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Description As a GPU Physical Verification engineer, you will work closely with the Physical Design team to drive physical verification aspects in the design cycle. You will work with physical design ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC ...

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$106 - $200/hr

In this role, you will collaborate with architects, RTL developers, and physical design teams to ... experience, internship experiences and or schoolwork/classes/research.Minimum Qualifications:

Intel

CPU Verification Engineer

Austin, TX · On-site

$105K - $200K/yr

In this role, you will collaborate with architects, RTL developers, and physical design teams to ... internship experiences and or schoolwork/classes/research. Minimum Qualifications: * Bachelor ...

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Internship Physical Verification Engineer information

What is the difference between Internship Physical Verification Engineer vs Internship Digital Verification Engineer?

AspectInternship Physical Verification EngineerInternship Digital Verification Engineer
Primary FocusVerifying physical chip layouts and manufacturing readinessVerifying digital circuit functionality and logic design
Required SkillsHardware design, physical design tools, layout verificationHardware description languages, simulation, testbench development
Work EnvironmentSemiconductor fabrication and physical design teamsASIC/FPGA design teams, digital logic development
Industry UsageVLSI, semiconductor manufacturingASIC, FPGA, digital IC design

Both roles are internship positions in the semiconductor industry, focusing on different aspects of chip design. The Physical Verification Engineer internship emphasizes physical layout and manufacturing checks, while the Digital Verification Engineer internship centers on verifying digital logic functionality. Candidates should have relevant technical skills in their respective areas, and both roles offer valuable experience in the semiconductor design process.

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Internship Physical Verification Engineer jobs near you

Principal Physical Verification Engineer

Celero Communications, Inc.

Austin, TX • On-site

$150K - $250K/yr

Full-time

Posted yesterday

New

Job description

Principal Full-Chip Physical Verification Engineer
Key Responsibilities
Team & Project Leadership
• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks
Physical Verification Ownership
• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules
Cross-Functional Collaboration
• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews
Required Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications
Proven hands-on experience with:
• Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV
Strong expertise in:
• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration
Preferred Qualifications
• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)