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Design Verification Jobs in California (NOW HIRING)

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

indie

Design Verification Engineer

Aliso Viejo, CA · On-site

$145K - $177K/yr

As a Design Verification Engineer, you will be responsible for developing and executing comprehensive verification strategies for next-generation automotive camera video and vision processors. You ...

Apple

Design Verification Lead

Cupertino, CA · On-site

$167K - $204K/yr

We are looking for a remarkable Design Verification Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of mobile solutions.

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$146K/yr

As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta's data center applications.

TylSemi

Design Verification Architect

San Jose, CA · On-site

$150K - $300K/yr

Role Overview We are seeking a highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next ...

Insilico

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Insilico

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

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All JobsDesign Verification JobsDesign Verification Jobs in California

Design Verification information

See California salary details

$104.1K

$147.2K

$164.8K

How much do design verification jobs pay per year?

As of Aug 9, 2026, the average yearly pay for design verification in California is $147,197.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $163,800.00 per year, depending on experience, location, and employer.

What is the difference between Design Verification vs Design Validation?

AspectDesign VerificationDesign Validation
PurposeEnsures the design meets specified requirements through testing and analysisConfirms the final product fulfills user needs and intended use
TimingDuring the development phaseAfter the product is developed and before release
MethodsInspections, reviews, testing, analysisUser testing, field trials, real-world testing
FocusDesign correctness and complianceProduct effectiveness and user satisfaction

While Design Verification checks if the design meets specified requirements during development, Design Validation ensures the final product performs effectively in real-world conditions. Both are essential steps in the product development process to deliver a reliable and user-centered product.

What is a design verification engineer?

Design verification engineers are professionals who ensure that hardware or software designs meet their intended specifications and function correctly before production or release. They develop and execute tests, write verification plans, create simulation environments, and identify design flaws or errors. Their work is critical in industries like semiconductor, electronics, and software development to prevent costly mistakes and ensure high-quality products. Design verification engineers often work closely with design and validation teams throughout the product development lifecycle.

What are the key skills and qualifications needed to thrive as a design verification engineer?

To thrive as a Design Verification Engineer, you need a solid background in digital design, verification methodologies, and programming languages like SystemVerilog, typically supported by a degree in electrical engineering or a related field. Familiarity with verification tools such as UVM, simulation environments, and EDA software is essential, along with knowledge of scripting languages like Python or Perl. Strong analytical thinking, attention to detail, and effective teamwork are standout soft skills in this role. These skills ensure accurate validation of complex hardware designs, reducing errors and supporting reliable product development cycles.

What are some common challenges faced by design verification engineers, and how can they be addressed?

Design Verification engineers often encounter challenges such as managing complex testbenches, debugging intricate corner cases, and ensuring coverage completeness within tight project timelines. To address these, it’s important to have strong scripting skills, collaborate closely with design and validation teams, and make effective use of verification methodologies like UVM. Regular communication and review cycles also help catch issues early and improve overall verification quality.
What are the most commonly searched types of Design Verification jobs in California? The most popular types of Design Verification jobs in California are:
What are popular job titles related to Design Verification jobs in California? For Design Verification jobs in California, the most frequently searched job titles are:
What job categories do people searching Design Verification jobs in California look for? The top searched job categories for Design Verification jobs in California are:
What cities in California are hiring for Design Verification jobs? Cities in California with the most Design Verification job openings:
Design Verification jobs near you
Infographic showing various Design Verification job openings in California as of August 2026, with employment types broken down into 77% Full Time, 2% Part Time, and 21% Contract. Highlights an 95% In-person, and 5% Hybrid job distribution, with an average salary of $147,197 per year, or $70.8 per hour.

Design Verification Engineer

Baidu USA

Sunnyvale, CA • On-site

$159K - $194K/yr

Full-time

Re-posted 28 days ago

Job description

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?
We're looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Description
We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.
Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
Qualifications
  • Minimum 5 years of experience of UVM based verification on a significantly complex project.
  • Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
  • Advanced knowledge of System Verilog and the UVM methodology.
  • Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
  • Good practice of one scripting language (Perl, Python, Tcl) no preference.
  • SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
  • Familiar with C/C++.
  • Formal Verification (Model Checking, Equivalence Checking).
  • Excellent communication skills in both English and Chinese.

Culture Fit:
  • Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
  • Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
  • Hungry to learn: We are eager to see you learn new skills and grow.
  • Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.

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