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System Verilog Jobs in California (NOW HIRING)

Planning the verification of complex digital systems * Creating a constrained-random verification environment using System Verilog and UVM * Identifying and writing all types of coverage measures for ...

Mixed Signal RTL Design Engineer

Cupertino, CA · On-site

$167K/yr

... System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm development Working experience with physical design teams Good Knowledge of front-end tools (Verilog simulators ...

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Key Skills Required · 8+ years of Design Verification experience in semiconductor/ASIC/SoC development. · Strong expertise in System Verilog. · Extensive experience with UVM (Universal ...

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

Expertise creating and using real-numbered analog behavioral models in System Verilog a plus. Wireless experience a plus Ability to work well in a team and be productive under aggressive schedule ...

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How much do system verilog jobs pay per year?

As of Aug 16, 2026, the average yearly pay for system verilog in California is $125,549.00, according to ZipRecruiter salary data. Most workers in this role earn between $96,700.00 and $154,900.00 per year, depending on experience, location, and employer.

What are the typical daily tasks and team interactions for a system verilog engineer?

SystemVerilog Engineers typically spend their days writing, debugging, and optimizing verification testbenches and scripts to ensure hardware designs function as intended. They often collaborate closely with design engineers, participating in design reviews, and providing feedback on specification documents. Frequent interactions with verification teams help in developing comprehensive test plans and resolving functional issues. The role requires proactive communication and teamwork, as successful verification projects depend on close cooperation between multiple engineering disciplines.

What jobs use System Verilog?

SystemVerilog is primarily used in roles related to hardware design and verification, such as FPGA and ASIC design engineers, verification engineers, and hardware developers. These jobs often require knowledge of digital design, simulation tools, and hardware description languages, and are common in semiconductor, electronics, and technology companies.

What are the key skills and qualifications needed to thrive in the system verilog position, and why are they important?

To thrive as a SystemVerilog Engineer, you should have a solid background in digital design, logic verification, and a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys VCS, Cadence Incisive, and UVM methodology is often required, along with relevant certifications or hands-on project experience. Strong analytical thinking, problem-solving, and effective communication are crucial soft skills for collaborating with design and verification teams. Mastery of these skills ensures robust and efficient verification processes, which are critical for delivering high-quality hardware designs on schedule.

What is a system verilog?

A SystemVerilog job typically involves designing, verifying, and testing digital hardware using the SystemVerilog language. Engineers in this role work on developing testbenches, writing assertions, and simulating circuits to ensure functional correctness. These jobs are common in semiconductor and ASIC/FPGA design industries, where verification engineers use SystemVerilog with methodologies like UVM. Strong knowledge of RTL design, verification methodologies, and debugging tools is essential.

What are the most commonly searched types of System Verilog jobs in California?

The most popular types of System Verilog jobs in California are:

What job categories do people searching System Verilog jobs in California look for?

The top searched job categories for System Verilog jobs in California are:

What cities in California are hiring for System Verilog jobs?

Cities in California with the most System Verilog job openings:

Infographic showing various System Verilog job openings in California as of August 2026, with employment types broken down into 1% As Needed, 82% Full Time, 13% Part Time, 2% Temporary, and 2% Contract. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $125,549 per year, or $60.4 per hour.

Design Verification Engineer-System Verilog/UVM

Advanced Micro Devices

San Jose, CA • On-site

$95 - $120/hr

Other

Re-posted 8 days ago


Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

27th of 157 rated electronics manufacturers


Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE

As a member of the Front-End Verification team, you will play a critical role in validating the functional correctness of next-generation AMD/Xilinx programmable devices. Working across a multi-site, global engineering organization, you will drive high-quality verification execution from feature definition through silicon readiness.

THE PERSON

You are passionate about digital design and advanced verification methodologies. You thrive in collaborative, cross-functional environments and communicate effectively across sites and time zones. With strong analytical and problem-solving skills, you take ownership of complex technical challenges and are motivated to continuously learn and improve.

KEY RESPONSIBILITIES
  • Collaborate with architects, hardware and firmware engineers to understand the new features to be verified
  • Take ownership of block level verification tasks
  • Define test plans, test benches, and tests using System Verilog and UVM
  • Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
  • Review functional and code coverage metrics to meet the coverage requirements
  • Develop and improve existing verification flows and environments
PREFERRED EXPERIENCE
  • Strong understanding of computer architecture and logic design
  • Knowledge of Verilog, System Verilog and UVM is a must
  • Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
  • Working knowledge of C/C++ and Assembly programming languages
  • Exposure to scripting (Python preferred) for post-processing and automation
  • Experience with gate level simulation, power and reset verification
ACADEMIC CREDENTIALS
  • Bachelor’s or Master’s degree in computer engineering, Electrical Engineering or a related field
LOCATION

San Jose, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s "Responsible AI Policy" is available here.

This posting is for an existing vacancy.

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