Electrical Design Engineer

Description:
Kronos has a long history of avionics engineering working with some of the largest aircraft integrators in the world. We always provide our partners with 100% customer satisfaction and on-time delivery. If you are excited about working for a company that takes its job seriously and does not cut corners you will have a home with Kronos.

Job Description:

We are seeking an experienced ASIC/FPGA Design Verification Engineer with UVM experience to join our team. In this role, you will work closely with design engineers to develop and execute comprehensive test plans for the verification of ASIC and FPGA designs. You will be responsible for creating test environments using the Universal Verification Methodology (UVM) and ensuring that designs meet functional specifications and performance goals.

• ASIC/FPGA Design Verification Engineer with UVM Experience
• Create UVM simulation plan from design specification.
• Create or modify UVC, Score Board, Monitor, and test cases.
• Verify until functional coverage and code coverage meet project threshold. Document results.

Responsibilities:

• Develop and execute verification plans for ASIC and FPGA designs.
• Design, implement, and maintain test environments using UVM.
• Create testbenches and reusable verification components to support simulation-based testing.
• Conduct functional, performance, and coverage-driven verification to ensure design correctness.
• Collaborate with design engineers to identify and resolve design issues.
• Debug simulation failures and provide detailed reports on findings.
• Analyze verification results and provide recommendations for design improvements.
• Keep abreast of the latest industry trends and best practices in verification methodologies.
• Participate in design reviews and provide feedback on verification aspects of the designs.
• Work in a collaborative environment and communicate effectively with cross-functional teams.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's degree preferred.
• Proven experience (3+ years) in ASIC/FPGA design verification using UVM.
• Strong understanding of digital design and verification principles.
• Proficiency in hardware description languages such as Verilog or VHDL.
• Proficiency in verification languages such as SystemVerilog.
• Experience with simulation tools such as ModelSim, VCS, or similar.
• Familiarity with coverage-driven verification and assertion-based verification.
• Excellent debugging and problem-solving skills.
• Strong analytical and communication skills.
• Ability to work effectively in a team-oriented environment.

Preferred Qualifications:

• Experience with scripting languages (e.g., Python, Perl) for automation.
• Knowledge of FPGA development and implementation flows.
• Familiarity with hardware/software co-verification.