Staff Physical Design Engineer

Job Title: Staff Physical Design Engineer
Location: Minneapolis MN 55413
Contract Start: June 15, 2026
Contract End: March 31, 2027
Engagement Type: Contract

Engagement Timeline

Phase

Dates

Activities

Onboarding

June 15 – June 30, 2026

Orientation, laptop/equipment delivery, IT setup, badge/access, PDK setup, team introductions

Design Execution

July 1 – March 31, 2027

Full PD ownership through GDSII tape-out sign-off

Contract End

March 31, 2027

Tape-out handoff, documentation closeout

About the Engagement

At Client, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.
Client’s Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions.
We are seeking an experienced contract Physical Design Engineer to own the complete back-end implementation of a high-speed interface test chip — from synthesized netlist through GDSII tape-out. This is a time-bound, high-impact engagement — not a staff augmentation role.
The target vehicle is a 36 I/O full-duplex die-to-die interconnect PHY test chip with integrated characterization functions including internal eye monitoring, internal error counting (PRBS-based), and I2C-based control and management. The PHY is largely custom-designed — this is a technically rich mixed-signal physical design challenge, not a macro-integration exercise. You will work in close collaboration with world-class analog designers, a 30-year layout veteran, and the digital Chip Lead, united around the goal of carrying this test chip to tape-out within the contract window.

About the Test Chip

The design target is a 36 I/O full-duplex PHY intended for die-to-die interconnect characterization. The PHY circuits are largely custom — developed in-house by Client’s Interface Pathfinding team to validate novel signaling architectures. The physical design challenge is substantive: mixed-signal floorplanning, analog/digital domain partitioning, high-speed I/O pad ring implementation, and full-chip timing closure in a constrained, analog-adjacent environment.
This is a characterization test chip, not a production device — the goal is to generate high-quality silicon data that validates novel PHY architectures for future die-to-die interconnect scaling.

What You’ll Own

• Floorplanning: Define and implement the full chip floorplan in close collaboration with the analog design team — including custom analog block placement, analog/digital partitioning, I/O ring architecture, power domain definition, and block-level area allocation.

• Power Planning: Design and implement the chip power distribution network (PDN); coordinate with the analog team on analog supply isolation, guard ring placement, and substrate noise considerations.

• Place & Route: Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and optimized database across all required corners and modes.

• Timing Closure: Own static timing analysis (Cadence Tempus) across all PVT corners and modes; identify and resolve timing violations through ECO, placement, and routing optimization; coordinate with the Chip Lead on constraint refinement.

• Power Integrity: Perform IR drop and electromigration analysis (Cadence Voltus or equivalent); identify and resolve PDN weaknesses.

• Physical Verification Sign-off: Execute and close DRC, LVS, and ERC to foundry-clean status using Mentor Calibre; manage waiver process for any non-cleanable violations.

• DFT Integration: Implement scan chain insertion and work with the Chip Lead on ATPG pattern generation and test coverage targets.

• Foundry Coordination: Interface with foundry on PDK questions, fill rule implementation, and tape-out submission requirements.

• Documentation: Maintain PD methodology documentation, floorplan rationale records, and ECO history to support program continuity and knowledge transfer at contract close. GDSII tape-out sign-off is the primary deliverable of this contract.

What You Bring

Required

• BS, MS, or PhD in Electrical Engineering or related field

• 8–15 years of physical design experience with at least one complete front-to-back tape-out as the primary or lead PD engineer

• Hands-on proficiency with Cadence Innovus for place-and-route — comfortable navigating complex placement constraints, congestion-driven routing, and post-route optimization without step-by-step guidance

• Hands-on proficiency with Cadence Tempus for static timing analysis including MMMC setup, OCV/AOCV analysis, and ECO-driven timing closure

• Hands-on proficiency with Mentor Calibre for DRC, LVS, and ERC sign-off

• Experience placing and integrating hard macros (analog PHY blocks, memory compilers, I/O cells) within a constrained mixed-signal floorplan

• Demonstrated ability to take broad ownership and drive to closure — comfortable leading implementation decisions, working across disciplines, and managing priorities without a large supporting PD organization

• Strong debugging and root-cause analysis skills — the ability to look at a failing DRC deck, a congested routing region, or a timing path that doesn’t respond to standard approaches and find a path forward

• Ability to hit the ground running — this engagement has a fixed end date tied to tape-out; ramp time is minimal by design

• Clear communicator across disciplines — able to discuss physical implementation constraints and their design implications with Chip Lead, analog designers, and verification engineers

Preferred

• Experience with mixed-signal or analog-adjacent chip physical design — including analog supply domain implementation, substrate isolation techniques, and analog/digital floor separation

• Familiarity with high-speed I/O pad ring design for differential full-duplex interfaces

• Experience with power domain implementation using UPF/CPF for multi-voltage PHY designs

• Proficiency with Cadence Voltus or Apache Redhawk for power integrity analysis

• Familiarity with Synopsys IC Compiler 2 (ICC2) as an alternative P&R environment

• Experience with signoff ECO flows — functional and metal-only ECOs post-tape-out

• Prior contract or startup experience — comfort operating where role boundaries are defined by program need rather than org chart

The Ownership Mindset

Because this role carries broad PD ownership on a lean team, we want to be explicit about what success looks like beyond the technical checklist:

• You identify problems before they become crises — reading timing reports, checking DRC incrementally, and monitoring IR drop throughout implementation rather than discovering issues at sign-off.

• You find creative solutions — when a standard fix doesn’t work in a mixed-signal context, you have the instinct and experience to try a non-obvious approach and the judgment to know when to bring the team in.

• You document your decisions — the implementation choices you make and the reasons behind them are institutional knowledge that must be captured and handed off at contract close, not carried in one person’s head.

Why This Engagement

• Broad ownership of the full physical implementation — from blank floorplan to GDSII — with visibility into every design decision along the way.

• You will work directly with world-class analog designers where the analog/digital co-design challenges are substantive and technically interesting.

• The team includes a 30-year layout veteran whose hands-on silicon experience is an extraordinary resource — the kind of pattern recognition and craft knowledge that no tool or textbook provides.

• The lean team structure means your contributions are visible, your judgment is trusted, and there is no queue of senior PD engineers ahead of you in the decision chain.

• The defined timeline and clear deliverables make this an ideal engagement for experienced contractors who thrive in focused, high-accountability environments.

A Note to All Candidates

This is not a staff augmentation engagement. We are seeking a contractor who can own the physical design function end-to-end for the duration of the program. If you are a senior PD engineer who has carried primary implementation responsibility on a chip before — and who found that experience energizing rather than overwhelming — we’d like to hear from you.