Uvm Verification Jobs in California (NOW HIRING)

Verification Engineer (UVM/SystemVerilog) 5 Work Location: El Segundo, CA Shift: First, 8:00 AM to 4:30 PM Possible OT opportunities Bachelor's Degree Active Secret Clearance required to start ...

Create test case and testbench with UVM methodology; full chip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification.

... UVM verification environments * C/C++ expertise * Excellent communication skills and a strong track record of cross-functional collaboration * Must have Experience with and understanding of common ...

Create test cases and test benches with UVM methodology. * Full chip/system functional verification by defining verification strategies, methodology, and test plans to enable effective verification.

Create testcase and testbench with UVM methodology * Fullchip/system functional verification, by defining verification strategies/methodologyand test plan to enable effective verification

Design and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components. * Develop directed and constrained-random ...

SystemVerilog + UVM verification,RTL blocks,VCS / Xcelium / Questa About the role: Design Verification engineer for wearables silicon accelerator IPs -- testbench development, coverage-driven ...

Design and implement IP or subsystem‑level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components. * Develop directed and ...

Architect and implement reusable SystemVerilog/UVM verification environments. Verify complex AXI4-based subsystems including: Multi-master/multi-slave configurations Outstanding transaction handling ...

Design and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components. * Develop directed and constrained-random ...

Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential. * Be familiar with hierarchical design approach, top‑down design, SoC and system level ...

Mandatory Areas Must Have Skills - FPGA Verification Engineer Skill 1 - 8 + Years of in FPGA Skill 2 - 5 +Years of Exp in UVM Skill 2 - 5 +Years of Exp in System Verlilog Location - Santa Clara, CA ...

The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have ...

Develop UVM verification environments, testbenches, test cases, and coverage models. * Automate verification scripts to improve efficiency and reduce development costs. * Simulate, integrate, verify ...

Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs * Develop verification plans with traceability to system and ...

... UVM Testbenches). Bring up GPUs, SOCs, Switch, NIC on emulation, root causing system level test ... Bring-up and verify High Speed protocols like PCIe/CXL/NVLINK/IB/Ethernet etc .... Low speed ...

Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential. * Be familiar with hierarchical design approach, top-down design, SoC and system level ...

You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure.

Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential. * Be familiar with hierarchical design approach, top-down design, SoC and system level ...

Qualifications * 8+ years of experience in UVM verification and UVM environment development (must have) * Proficient in test plan definition and testcase development in C/Assembly/System Verilog