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Ic Packaging Engineer Jobs (NOW HIRING)

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating ...

Falcomm

Senior IC Packaging Designer

Atlanta, GA · On-site

$98K - $104K/yr

The position requires close collaboration with RFIC designers, layout engineers, testing teams, and ... IC packaging. * Must be willing to work full-time, onsite, in Atlanta, GA. Preferred Skills:

Apple

IC Packaging Simulation Engineer

Austin, TX

$129K - $225K/yr

We are looking for a self-motivated Packaging Simulation Engineer who is proficient in FEM ... Description • In this role, you will be working on stress and deformation simulation of IC ...

Apple

IC Packaging Simulation Engineer

Austin, TX

$184K - $324K/yr

We are looking for a self-motivated Packaging Simulation Engineer who is proficient in FEM ... Description In this role, you will be working on stress and deformation simulation of IC packages ...

Falcomm

Senior IC Packaging Designer

Atlanta, GA

$98K - $104K/yr

The position requires close collaboration with RFIC designers, layout engineers, testing teams, and ... IC packaging. * Must be willing to work full-time, onsite, in Atlanta, GA. Preferred Skills:

Apple

IC Packaging Simulation Engineer

Austin, TX

$184K - $324K/yr

We are looking for a self-motivated Packaging Simulation Engineer who is proficient in FEM ... Description In this role, you will be working on stress and deformation simulation of IC packages ...

Falcomm

Senior IC Packaging Designer

Atlanta, GA · On-site

$98K - $104K/yr

The position requires close collaboration with RFIC designers, layout engineers, testing teams, and ... IC packaging. * Must be willing to work full-time, onsite, in Atlanta, GA. Preferred Skills:

Apple

IC Packaging Simulation Engineer

Austin, TX

$129K - $225K/yr

We are looking for a self-motivated Packaging Simulation Engineer who is proficient in FEM ... Description • In this role, you will be working on stress and deformation simulation of IC ...

Skyworks

Sr. Packaging Engineer

Irvine, CA · On-site

$91K - $177K/yr

Sr. Packaging Engineer Posting Start Date: 6/22/26 Job Location(s): Irvine If you are looking for a ... Requisition ID: 77803 Description In this role, candidate will manage and execute IC Packaging ...

Apple

Packaging Assembly Engineer

Austin, TX

$184K - $324K/yr

We are looking for a hardworking and passionate IC Packaging Assembly Engineer to join our team. In this highly visible role, you will own development, optimization and sustaining the advanced flip ...

Phix

Senior Photonics Packaging Engineer

Bozeman, MT · On-site

$106K - $146K/yr

As a Senior Photonics Engineer specializing in Photonic IC Packaging, you are a technical leader responsible for designing, developing, and scaling advanced photonic packaging solutions. You drive ...

Apple

Packaging Assembly Engineer

Austin, TX

$184K - $324K/yr

We are looking for a hardworking and passionate IC Packaging Assembly Engineer to join our team. In this highly visible role, you will own development, optimization and sustaining the advanced flip ...

Apple

IC Package Integration Lead

San Francisco, CA · On-site

We are looking for a hardworking, and passionate IC Packaging Engineering Lead to join our team. Description • Work with cross-functional teams and lead package integration and architecture efforts ...

Apple

IC Package Integration Lead

Austin, TX · On-site

We are looking for a hardworking, and passionate IC Packaging Engineering Lead to join our team. Description • Work with cross-functional teams and lead package integration and architecture efforts ...

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Ic Packaging Engineer information

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How much do ic packaging engineer jobs pay per hour?

As of Jul 24, 2026, the average hourly pay for ic packaging engineer in the United States is $42.37, according to ZipRecruiter salary data. Most workers in this role earn between $32.69 and $49.28 per hour, depending on experience, location, and employer.

What is an IC Packaging Engineer job?

An IC Packaging Engineer is responsible for designing and developing semiconductor packaging solutions to ensure the performance, reliability, and manufacturability of integrated circuits (ICs). They work closely with design, manufacturing, and testing teams to create packaging that meets thermal, electrical, and mechanical requirements. Their role includes material selection, process optimization, and collaboration with suppliers to enhance packaging efficiency and cost-effectiveness.

What are the key skills and qualifications needed to thrive in the Ic Packaging Engineer position, and why are they important?

To thrive as an IC Packaging Engineer, you need a robust background in materials science, semiconductor device physics, and mechanical or electrical engineering, typically supported by a relevant engineering degree. Proficiency in design and simulation tools like Cadence, ANSYS, and industry standards such as JEDEC, along with knowledge of thermal, electrical, and reliability testing methods, is essential. Effective communication, cross-functional teamwork, and strong problem-solving skills help you excel in project-based environments. These qualifications are critical for delivering reliable, high-performance integrated circuit packages essential to the semiconductor industry's success.

What are the typical daily responsibilities of an IC Packaging Engineer?

IC Packaging Engineers typically focus on designing, developing, and testing packaging solutions for integrated circuits, working closely with cross-functional teams including design, process, and reliability engineers. Day-to-day tasks may include creating layout drawings, performing simulations, evaluating material choices, resolving technical challenges during assembly, and interacting with manufacturing partners. They are responsible for ensuring the package design meets performance, cost, and reliability requirements set by customers or the market. This role often involves regular collaboration and problem-solving to meet tight development timelines and maintain product quality.

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What cities are hiring for Ic Packaging Engineer jobs? Cities with the most Ic Packaging Engineer job openings:
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Ic Packaging Engineer jobs near you
Infographic showing various Ic Packaging Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $88,120 per year, or $42.4 per hour.

IC Package Engineer

Etched

Cupertino, CA • On-site

$2.0K/mo

Full-time

Medical, Dental, Vision

Posted 16 hours ago

Job description

About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.
IC Package Engineer
We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive experience with advanced packaging technologies such as CoWoS, large-scale BGA designs, and package warpage mitigation strategies. You will play a key role in ensuring the mechanical and electrical integrity of packages that power the next generation of AI hardware.
Representative Projects:
  • Own the end-to-end package design process, including substrate layout and IC package design, while collaborating with internal teams and external vendors to deliver optimized, manufacturable solutions
  • Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating stiffeners as needed
  • Expertise in large-scale BGA design, including experience with packages exceeding 4000-ball arrays, ball pitch optimization, routing, and power/ground plane design
  • Conduct mechanical and warpage analysis to address package warpage and coplanarity requirements across varying package sizes, collaborating with mechanical teams for simulation and testing to minimize thermal and mechanical stress
  • Perform design validation by assessing package layouts against electrical and mechanical constraints, providing design reviews and guidance on substrate and interconnect solutions, while archiving DFM-related learning for continuous improvement opportunities
  • Collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams to ensure holistic package solutions, while interfacing with vendors to align design requirements and production feasibility
  • Oversee package reliability testing, including thermal, warpage, shock, shear, HTSL, HAST, ALT, JESD22, and electrical tests, while interfacing with various vendors to ensure compliance and quality

You maybe a good fit if you have
  • Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, or related discipline
  • 5+ years of experience in advanced IC package design, including CoWoS or equivalent technologies
  • Proven experience in substrate layout and BGA package design for large ball arrays (>4000 balls) with >20Ghz signaling and >500W
  • Strong understanding of stiffener design, open vs. closed package requirements, and package warpage and coplanarity challenges across various sizes
  • Proficiency in package design tools such as Cadence APD/SIP, Mentor Xpedition, or similar
  • Familiarity with mechanical stress analysis, simulation, and validation methodologies
  • Solid communication skills to work across multi-disciplinary teams and external partners
  • Experience with advanced packaging nodes (e.g., 2.5D/3D stacking)
  • Knowledge of thermal management techniques in package design
  • Previous experience working in AI, HPC, or semiconductor design companies

We encourage you to apply even if you do not believe you meet every single qualification.
How we're different:
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Benefits:
  • Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino

Apply