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Ic Packaging Engineer Jobs (NOW HIRING)

Qualcomm

Staff IC Packaging Engineer

San Diego, CA · On-site

We are seeking a highly motivated Staff IC Packaging Engineer to lead the development and commercialization of advanced integrated circuit (IC) packaging technologies. This role focuses on driving ...

Qualcomm

Principal IC Packaging Engineer

San Diego, CA · On-site

We are seeking a highly motivated Principal IC Packaging Engineer to lead the development of advanced integrated circuit (IC) packaging technologies. This role focuses on spearheading new product ...

Axiado

Senior IC Packaging Engineer

San Jose, CA · On-site

$122K - $168K/yr

Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup ...

Axiado

Senior IC Packaging Engineer

San Jose, CA

$122K - $168K/yr

Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup ...

Apple

IC Packaging Integration Engineer

Austin, TX · On-site

We are looking for versatile and passionate IC Packaging Engineer to join our team! • You will be responsible for IC packaging development • Work with cross-functional teams and lead SoC Package ...

Apple

IC Packaging Integration Engineer

Austin, TX

$181K - $318K/yr

We are looking for versatile and passionate IC Packaging Engineer to join our team! Description • You will be responsible for IC packaging development • Work with cross-functional teams and lead ...

Apple

IC Packaging Integration Engineer

Austin, TX

$181K - $318K/yr

We are looking for versatile and passionate IC Packaging Engineer to join our team! Description • You will be responsible for IC packaging development • Work with cross-functional teams and lead ...

Broadcom, Inc.

IC Package Design / Development

San Jose, CA · On-site

$108K - $192K/yr

... IC Packaging Engineer to drive next-generation package architecture, design, and productization ... using advanced node silicon (7nm, 5nm, 3nm and beyond). This role partners closely with chip design ...

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How much do ic packaging engineer jobs pay per hour?

As of Jun 8, 2026, the average hourly pay for ic packaging engineer in the United States is $42.37, according to ZipRecruiter salary data. Most workers in this role earn between $32.69 and $49.28 per hour, depending on experience, location, and employer.

What is an IC Packaging Engineer job?

An IC Packaging Engineer is responsible for designing and developing semiconductor packaging solutions to ensure the performance, reliability, and manufacturability of integrated circuits (ICs). They work closely with design, manufacturing, and testing teams to create packaging that meets thermal, electrical, and mechanical requirements. Their role includes material selection, process optimization, and collaboration with suppliers to enhance packaging efficiency and cost-effectiveness.

What are the key skills and qualifications needed to thrive in the Ic Packaging Engineer position, and why are they important?

To thrive as an IC Packaging Engineer, you need a robust background in materials science, semiconductor device physics, and mechanical or electrical engineering, typically supported by a relevant engineering degree. Proficiency in design and simulation tools like Cadence, ANSYS, and industry standards such as JEDEC, along with knowledge of thermal, electrical, and reliability testing methods, is essential. Effective communication, cross-functional teamwork, and strong problem-solving skills help you excel in project-based environments. These qualifications are critical for delivering reliable, high-performance integrated circuit packages essential to the semiconductor industry's success.

What are the typical daily responsibilities of an IC Packaging Engineer?

IC Packaging Engineers typically focus on designing, developing, and testing packaging solutions for integrated circuits, working closely with cross-functional teams including design, process, and reliability engineers. Day-to-day tasks may include creating layout drawings, performing simulations, evaluating material choices, resolving technical challenges during assembly, and interacting with manufacturing partners. They are responsible for ensuring the package design meets performance, cost, and reliability requirements set by customers or the market. This role often involves regular collaboration and problem-solving to meet tight development timelines and maintain product quality.

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Ic Packaging Engineer jobs near you
Infographic showing various Ic Packaging Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 54% Full Time, 3% Part Time, 1% Temporary, 38% Contract, and 3% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $88,120 per year, or $42.4 per hour.

Senior IC Packaging Engineer

Aziro Technologies LLC

San Jose, CA

Other

Posted 27 days ago

Job description

Job title: Senior IC Packaging Engineer

Location: San Jose, CA, USA

Duration: Full-time

Department: Design

Job Description

Client is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings.

You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp. You will work closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.

Key Responsibilities

  • Serve as technical authority for IC and SiP packaging across multiple products and programs.
  • Own package architecture and technology roadmap, aligned with product, cost, and scalability goals.
  • Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
  • Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces.
  • Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
  • Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels.
  • Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness.
  • Influence product roadmap, risk management, and investment decisions through technical insight.
  • Establish scalable design methodologies, best practices, and reusable packaging flows.

Qualifications

  • BSEE or MSEE (PhD a plus) in Electrical Engineering, or related field.
  • Minimum of 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products.
  • Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe)
  • Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, Advanced packaging materials and substrate technologies, Design-for-Manufacturing (DFM) and yield optimization
  • Demonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment.

Required Experience

  • Technical leadership of multiple end-to-end packaging programs, from early architecture through high-volume production.
  • Proven experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5 / LPDDR5X, USB 3.x or 10G interfaces
  • Experience defining die-to-die and chiplet based RDL/bump architecture.
  • Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp.
  • Strong cross-functional leadership across design, product, test, operations, reliability, and customer teams.
  • Clear understanding of cost, yield, schedule, and risk trade-offs at a product and portfolio level.

Tools & Preferred Skills

  • Cadence Allegro Package Designer (APD) or equivalent EDA tools.
  • Strong background in flip-chip BGA package design and layout.
  • SI/PI expertise preferred, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
  • Experience building new packaging methodologies or platforms from scratch.

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