RTL Design Engineer
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...
RTL Design Engineer
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...
ASIC Design Verification Engineer - New College Grad 2026
Austin, TX · On-site
$134K - $164K/yr
The NVIDIA System-On-Chip (SOC) group is looking for an entry level ASIC Verification Engineer! In ... Strong understanding of RTL design (Verilog). * Good understanding of computer architecture ...
ASIC Design Verification Engineer - New College Grad 2026
Austin, TX · On-site
$134K - $164K/yr
The NVIDIA System-On-Chip (SOC) group is looking for an entry level ASIC Verification Engineer! In ... Strong understanding of RTL design (Verilog). * Good understanding of computer architecture ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...
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SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
Irvine, CA · On-site
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$120K - $210K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$171K - $302K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
FPGA Engineer with Security Clearance
$131K - $180K/yr
... FPGA/ASIC digital architectures - RTL design and implementation in VHDL or Verilog - Timing ... Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL ...
FPGA Engineer with Security Clearance
$131K - $180K/yr
... FPGA/ASIC digital architectures - RTL design and implementation in VHDL or Verilog - Timing ... Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL ...
SerDes RTL Design Engineer
San Jose, CA · On-site
$145K/yr
AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. THE ...
SerDes RTL Design Engineer
San Jose, CA · On-site
$145K/yr
AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. THE ...
We are looking for an ASIC Clocks Design Engineer to join the team. Our team crafts all aspects of ... Experience in RTL design (Verilog), verification and logic synthesis. * Strong coding skills in ...
We are looking for an ASIC Clocks Design Engineer to join the team. Our team crafts all aspects of ... Experience in RTL design (Verilog), verification and logic synthesis. * Strong coding skills in ...
RTL Design Engineering Intern
Camarillo, CA · On-site
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
RTL Design Engineering Intern
Camarillo, CA · On-site
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
FPGA/ASIC Design Engineer (Silicon Engineering)
Redmond, WA · On-site
$145K - $195K/yr
... in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: * ASIC/FPGA ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
FPGA/ASIC Design Engineer (Silicon Engineering)
Redmond, WA · On-site
$145K - $195K/yr
... in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: * ASIC/FPGA ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
FPGA/ASIC Design Engineer (Silicon Engineering)
Redmond, WA · On-site
$140K - $175K/yr
... in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: * ASIC/FPGA ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
FPGA/ASIC Design Engineer (Silicon Engineering)
Redmond, WA · On-site
$140K - $175K/yr
... in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: * ASIC/FPGA ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic ...
As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic ...
Entry Level Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do entry level asic rtl design engineer jobs pay per year?
As of Jun 20, 2026, the average yearly pay for entry level asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?
Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.
What does an Entry Level ASIC RTL Design Engineer do?
An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.
What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?
To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.
What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Entry Level Asic Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL) | Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required |
| Work Environment | Semiconductor companies, chip design teams, hardware development labs | Electronics companies, integrated circuit design teams, hardware development labs |
| Industry Usage | Primarily in ASIC/FPGA chip design | In digital hardware design across various sectors including consumer electronics and telecom |
While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.
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$105K - $200K/yr
Full-time
Medical, Retirement, PTO
Posted yesterday
Intel rating
8.8
Based on 143 frontline employees who took The Breakroom Quiz
8th of 139 rated electronics manufacturers
Job description
Job Details:Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure highquality integration of the CPU block.Qualifications:Minimum QualificationsThe candidate must have a Bachelor's Degree in Electrical or Computer Engineering or any STEM related education with at least 2+ years of experience -OR- Master's Degree in Electrical or Computer EngineeringAt least 1+ years of coursework or experience in the following areas:oBasic Logic DesignoMicroprocessorsoComputer ArchitectureoDigital design and RTL codingoVerilog/SystemVerilog and/or VHDLoSynthesis tools (Design Compiler, Genus)oScripting languages (Python, Perl, TCL)Preferred QualificationsExperience with advanced verification methodologies (UVM, OVM)Knowledge of low-power design techniquesUnderstanding of physical design constraints and timing closureExperience with version control systems (Git, Perforce)Experience with simulation tools (ModelSim, VCS, Xcelium)Job Type:College GradShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968