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Entry Level Asic Rtl Design Engineer Jobs in Ann Arbor, MI

Senior Fpga Engineer

Southfield, MI ยท Hybrid

$100 - $110/hr

Job Title: Senior FPGA Engineer This role focuses on designing and implementing FPGA-based ... Proven experience in FPGA or ASIC design and RTL implementation. * Solid understanding of DSP ...

Design Southeast Michigan's Future From a Pretty Cool Office MSG is growing, and we're looking for ... entry-level experience. Over six months, you'll take part in a hands-on curriculum covering ...

Design Southeast Michigan's Future From a Pretty Cool Office MSG is growing, and we're looking for ... entry-level experience. Over six months, you'll take part in a hands-on curriculum covering ...

Entry Level Electrical Engineer

Detroit, MI ยท On-site

$62K - $69K/yr

SmithGroup is an integrated design firm with a reputation for cultivating a top-ranked culture ... The Detroit office of SmithGroup is looking for a Entry Level Electrical Engineer to join our team.

Civil Engineer

Detroit, MI ยท On-site

$28 - $32/hr

Design Southeast Michigan's Future From a Pretty Cool Office MSG is growing, and we're looking for ... entry-level experience. Over six months, you'll take part in a hands-on curriculum covering ...

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Entry Level Controls Engineer

Detroit, MI ยท On-site

$82K - $106K/yr

*Must be okay with travel Entry Level Position: College Graduate - 2 years experience This is a ... Design and develop electrical control systems that will interface with facility & building ...

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Entry Level Asic Rtl Design Engineer information

See Ann Arbor, MI salary details

$92K

$146.9K

$197.6K

How much do entry level asic rtl design engineer jobs pay per year?

As of Jul 29, 2026, the average yearly pay for entry level asic rtl design engineer in Ann Arbor, MI is $146,941.00, according to ZipRecruiter salary data. Most workers in this role earn between $128,600.00 and $176,100.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Ann Arbor, MI? The most popular types of Asic Rtl Design Engineer jobs in Ann Arbor, MI are:
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Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Ann Arbor, MI as of July 2026, with employment types broken down into 100% Full Time. Highlights an 87% In-person, and 13% Hybrid job distribution, with an average salary of $146,941 per year, or $70.6 per hour.
SystemC Modelling Engineer

SystemC Modelling Engineer

Pi Square Technologies LLC

Farmington Hills, MI โ€ข On-site

$98K - $134K/yr

Full-time

Posted 9 hours ago


Job description

SystemC Modelling Engineer
Description:
  • Will be responsible for developing and maintaining high-fidelity system-level models using SystemC for hardware/software co-design and verification.
  • This role is crucial for enabling early performance analysis, architecture exploration, and functional validation of complex embedded systems.
  • The engineer will work closely with architecture, design, and verification teams to ensure the accuracy and efficiency of the SystemC models.
  • Projects will involve modeling various components of a platform, including processors, memory subsystems, and peripherals.
  • The candidate will utilize SystemC and related simulation environments.

Key Roles & Responsibilities:
  • Develop and maintain accurate and efficient SystemC models of platform components, including processors, memory controllers, and peripherals.
  • Implement TLM-based interfaces for communication between SystemC models and other simulation environments.
  • Validate the accuracy of SystemC models through comparison with RTL simulations and hardware prototypes, achieving a model fidelity target of X% (define target).
  • Collaborate with architecture and design teams to define modeling requirements and ensure models accurately reflect system specifications.
  • Contribute to the development of SystemC modeling guidelines and best practices within the organization.
  • Create and maintain documentation for SystemC models, including model descriptions, usage examples, and validation reports.
  • Debug and resolve issues identified during SystemC simulation, improving model performance and stability, reducing simulation time by X%.
  • Participate in code reviews and provide constructive feedback to other engineers.

Required Skills:
  • SystemC & TLM (Transaction Level Modeling)
  • C++ (Proficient level, including object-oriented design principles)
  • Hardware Description Languages (HDLs): VHDL or Verilog (Understanding and ability to interface with)
  • Debugging Tools (e.g., GDB, DVE)
  • Scripting Languages (Python, Perl, or similar)
  • Version Control Systems (Git)
  • Embedded Systems Architecture (Understanding of processor architectures, memory hierarchies, and bus protocols)
  • Communication (Excellent written and verbal communication skills)
  • Problem-Solving (Strong analytical and problem-solving abilities)
  • Team Collaboration (Ability to work effectively in a team environment)
  • Defining transaction level models of non-memory mapped interfaces (I2C, SPI, USB, CAN, Ethernet etc.)
  • Porting the embedded operating system (Linux, VxWorks, Android ) on the virtual prototype, developing the device drivers etc.
  • Verification of models at IP & SoC level.
  • Develop regress able self-checking test suites using C/ARM assembly.
  • Develop System Level Flows and Methodologies using virtual prototypes

Desired Skills:
  • Experience with Board bring-up, platform initialization, board support package development, peripherals such as PCIe, I2C, SPI, USB, UART , OS primitives, memory management, scheduling, interrupts, and multi-threading.
  • Good experience in system level debugging with comprehensive understanding of managing and prioritizing system level issues.
  • Extensive background in firmware development or embedded software development within a multicore environment or hardware context.