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Entry Level Asic Rtl Design Engineer Jobs in Newark, NJ

Amerlux

Entry Level Design Engineer

Oakland, NJ

... a Entry Level Design Engineer to join our team in our Oakland NJ facility. This is a great opportunity for a recent college graduate looking to being their career. This position requires being on ...

Amerlux

Entry Level Design Engineer

Oakland, NJ · On-site

$55K - $62K/yr

... a Entry Level Design Engineer to join our team in our Oakland NJ facility. This is a great opportunity for a recent college graduate looking to being their career. This position requires being on ...

Citadel Securities

FPGA Engineer (Intern)

Manhattan, NY

$4K - $4K/wk

FPGA Engineers work closely with business leaders to design and deploy FPGA solutions that help ... Experienced in RTL Design (SystemVerilog preferred). Python, C, Tcl, and Bash a plus. * Experience ...

Jane Street

FPGA Engineer

New York, NY

$142K - $182K/yr

Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ... A top-notch programmer with a love for technology * Comfortable with a software programming ...

Jane Street

FPGA Engineer

New York, NY · On-site

$142K - $182K/yr

Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ... A top-notch programmer with a love for technology * Comfortable with a software programming ...

SKF Group

Product Design Engineer

New York, NY

$141K - $169K/yr

We are seeking an experienced professional, but we will also consider entry-level applicants with the necessary skillsets. This engineer manages the technical design and CAD functions within the ...

Ciena

Digital Verification Engineer Expert

New York, NY · On-site

$147K - $234K/yr

ASIC Engineer (Digital Verification Engineer Expert (P4)) How You Will Contribute: The Wavelogic ... You would also be responsible for participating in architectural and design reviews to proactively ...

Ciena

Digital Verification Engineer Expert

Manhattan, NY · On-site

$147K - $234K/yr

ASIC Engineer (Digital Verification Engineer Expert (P4)) How You Will Contribute: The Wavelogic ... You would also be responsible for participating in architectural and design reviews to proactively ...

Qube Research & Technologies

FPGA Engineer

New York, NY · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

Qube Research & Technologies

FPGA Engineer

New York, NY · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

Dewberry

Entry Level Civil Engineer

Manhattan, NY

$81K - $83K/yr

Dewberry is currently seeking an Entry Level Civil Engineer to join our Civil Group in our New York ... Prior relevant internship or professional experience in site/civil design, including site planning ...

Dewberry

Entry Level Civil Engineer

Manhattan, NY · On-site

$81K - $83K/yr

Dewberry is currently seeking an Entry Level Civil Engineer to join our Civil Group in our New York ... Prior relevant internship or professional experience in site/civil design, including site planning ...

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All JobsEntry Level Asic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer Jobs in Newark, NJ

Entry Level Asic Rtl Design Engineer information

See Newark, NJ salary details

$98.3K

$157.1K

$211.2K

How much do entry level asic rtl design engineer jobs pay per year?

As of Jun 13, 2026, the average yearly pay for entry level asic rtl design engineer in Newark, NJ is $157,063.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,500.00 and $188,200.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

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Entry Level Asic Rtl Design Engineer jobs near you

Semiconductor Design Expert - AI Hardware

Mercor

New York, NY • On-site, Remote

$100/hr

Full-time

Posted 17 days ago

Job description

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Position: Electrical Engineering Expert (Semiconductor / ASIC / RFIC)
Type: Contract
Compensation: $100/hour
Location: Remote
Commitment: 15–20 hours/week

Role Responsibilities

  • Contribute expertise across Analog, Mixed-Signal, RFIC, ASIC, or Physical Design workflows.
  • Review semiconductor architectures, implementation methodologies, and silicon design tradeoffs.
  • Support tasks related to tapeout flows, verification, timing closure, and silicon validation.
  • Assist in evaluating and improving AI systems trained on hardware engineering workflows.
  • Provide technical insight based on real-world production silicon experience.

Qualifications

Must-Have

  • Hands-on ownership of chip blocks/systems through tapeout.
  • Experience with advanced semiconductor PDKs such as TSMC, GlobalFoundries, Samsung, or Intel.
  • Familiarity with pre- and post-silicon development flows.
  • Strong understanding of schematic design, simulation, verification, DRC/LVS, parasitic extraction, and silicon bring-up.
  • Prior experience in at least one of the following:
  • Analog/Mixed-Signal Design (ADCs, PLLs, LDOs, SerDes, PMICs, sensor interfaces)
  • RFIC Design (LNAs, mixers, transceivers, PLLs, PAs, mmWave systems)
  • ASIC/Physical Design (RTL, synthesis, STA, floorplanning, CTS, PnR, ECO flows)

Preferred

  • Production silicon experience preferred over purely academic or simulation-based work.
  • Experience taping out RF designs at GHz/mmWave frequencies.
  • Strong ability to explain architectural, power, performance, and timing tradeoffs made during implementation.
  • Experience working on advanced-node semiconductor designs.
  • Prior exposure to AI hardware, accelerators, or high-performance compute systems.

Application Process (Takes 20–30 mins to complete)

  • Upload resume
  • AI interview based on your resume
  • Submit form

Resources & Support

  • For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
  • For any help or support, reach out to: support@mercor.com

PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.