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Entry Level Asic Rtl Design Engineer Jobs in Newark, NJ

Jane Street

Hardware Engineer (FPGA/ASIC)

New York, NY · On-site

... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

Ciena Corporation

THW Client Co-op

New York, NY · On-site

$27 - $37.50/hr

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...

Ciena

THW Client Co-op

Manhattan, NY · On-site

$27 - $37.50/hr

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...

Amerlux

Entry Level Design Engineer

Oakland, NJ · On-site

... a Entry Level Design Engineer to join our team in our Oakland NJ facility. This is a great opportunity for a recent college graduate looking to being their career. This position requires being on ...

Amerlux

Entry Level Design Engineer

Oakland, NJ · On-site

$55K - $62K/yr

... a Entry Level Design Engineer to join our team in our Oakland NJ facility. This is a great opportunity for a recent college graduate looking to being their career. This position requires being on ...

Citadel Securities

FPGA Engineer (Intern)

Manhattan, NY · On-site

$4.3K - $4.8K/wk

FPGA Engineers work closely with business leaders to design and deploy FPGA solutions that help ... Experienced in RTL Design (SystemVerilog preferred). Python, C, Tcl, and Bash a plus. * Experience ...

Jane Street

FPGA Engineer

New York, NY

$142K - $182K/yr

Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ... A top-notch programmer with a love for technology * Comfortable with a software programming ...

Jane Street

FPGA Engineer

New York, NY · On-site

$142K - $182K/yr

Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ... A top-notch programmer with a love for technology * Comfortable with a software programming ...

SKF Group

Product Design Engineer

New York, NY

$141K - $169K/yr

We are seeking an experienced professional, but we will also consider entry-level applicants with the necessary skillsets. This engineer manages the technical design and CAD functions within the ...

Dewberry

Entry Level Electrical Engineer

Manhattan, NY · On-site

$80K - $83K/yr

Dewberry is currently seeking an Entry Level Electrical Engineer for our NYC office ... Duties will include building information modeling (BIM) and AutoCad drafting, design, drawing ...

Qube Research & Technologies

FPGA Engineer

New York, NY · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

Qube Research & Technologies

FPGA Engineer

New York, NY · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

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All JobsAsic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer Jobs in Newark, NJ

Entry Level Asic Rtl Design Engineer information

See Newark, NJ salary details

$98.3K

$157.1K

$211.2K

How much do entry level asic rtl design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for entry level asic rtl design engineer in Newark, NJ is $157,063.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,500.00 and $188,200.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

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Entry Level Asic Rtl Design Engineer jobs near you
Hardware Engineer (FPGA/ASIC)

Hardware Engineer (FPGA/ASIC)

Jane Street

New York, NY • On-site

Full-time

Posted 3 days ago

New

Job description

About the Position
Our goal is to give you a real sense of what it's like to work at Jane Street full time while also providing a truly unparalleled educational experience. As an intern, you are paired with full-time employees who act as mentors, collaborating with you on real-world projects we actually need done.
In this internship, you'll learn how we use tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our hardware engineering work, and we're looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you'll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.
The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background and experience, we'll craft a project that gives you exposure to our shared Hardcaml tech stack, as well as targeting an FPGA or ASIC platform.
During the program, you'll dive deep on one project, mentored closely by the full-time employees who helped design it. Some intern projects consider big-picture questions that we're still trying to figure out, while others involve building something new. Your mentors will help you gain a better understanding of the wide range of problems we solve every day. We expect interns to build hardware applications from concept to a working design; your projects will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration.
If you'd like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode. You can also learn more about Jane Street's internship program here.
About You
We don't expect you to have a background in finance, OCaml, functional programming, or any other specific field- we're looking for smart people who enjoy solving interesting problems. We're more interested in how you think and learn than what you currently know. You should be:
  • Comfortable with a software programming language
  • Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
  • Experienced working with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus for ASICs
  • Experienced with building a working hardware project (either FPGA or ASIC) through an academic, professional, or personal project
  • Interested in learning how to use FPGAs or ASICs in the context of networking

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