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Entry Level Asic Rtl Design Engineer Jobs in Los Angeles, CA

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Debug SoC Design Engineer

Irvine, CA · On-site

$146K - $178K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

You will provide high-quality RTL description, including assertions, for the design. Use formal ... Electrical Engineering. Pay & Benefits At Apple, base pay is one part of our total compensation ...

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Entry Level Asic Rtl Design Engineer information

See Los Angeles, CA salary details

$101.3K

$161.8K

$217.7K

How much do entry level asic rtl design engineer jobs pay per year?

As of Jul 31, 2026, the average yearly pay for entry level asic rtl design engineer in Los Angeles, CA is $161,837.00, according to ZipRecruiter salary data. Most workers in this role earn between $141,700.00 and $194,000.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Los Angeles, CA? The most popular types of Asic Rtl Design Engineer jobs in Los Angeles, CA are:
What are popular job titles related to Entry Level Asic Rtl Design Engineer jobs in Los Angeles, CA? For Entry Level Asic Rtl Design Engineer jobs in Los Angeles, CA, the most frequently searched job titles are:
What job categories do people searching Entry Level Asic Rtl Design Engineer jobs in Los Angeles, CA look for? The top searched job categories for Entry Level Asic Rtl Design Engineer jobs in Los Angeles, CA are:
What cities near Los Angeles, CA are hiring for Entry Level Asic Rtl Design Engineer jobs? Cities near Los Angeles, CA with the most Entry Level Asic Rtl Design Engineer job openings:
Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Los Angeles, CA as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $161,837 per year, or $77.8 per hour.

RTL Design Engineer (Silicon Engineering)

SpaceX

Irvine, CA

$145K - $195K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 14 days ago


SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

14th of 71 rated aerospace companies


Job description

RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog
  • Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
  • Engage in high-level architectural design for FPGA and ASICs
  • Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more

BASIC QUALIFICATIONS:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:

  • Master's in Electrical/Computer Engineering or related field
  • ASIC/FPGA system integration experience
  • Proficiency in Python for scripting
  • Experience in designing DSP or digital communication system datapath blocks
  • Experience with EDA tools such as HDL simulators
  • Experience and understanding of AXI/AHB/APB protocols
  • Strong foundation in electrical engineering fundamentals
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Demonstrated ability to work in a highly cross-functional role
  • Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:    

ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year    
ASIC Design Engineer/Level II: $145,000.00 - $195,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.


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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US