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Entry Level Asic Rtl Design Engineer Jobs in Fresno, CA

Hudson River Trading

AI Researcher

London, CA · On-site

Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch ... ASIC experience, HPC experience. The estimated base salary range for this position is 200,000 to ...

All JobsAsic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer Jobs in Fresno, CA

Entry Level Asic Rtl Design Engineer information

See Fresno, CA salary details

$93.3K

$149.1K

$200.6K

How much do entry level asic rtl design engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for entry level asic rtl design engineer in Fresno, CA is $149,131.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,600.00 and $178,700.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by entry level ASIC RTL design engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an entry level ASIC RTL design engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an entry level ASIC RTL design engineer?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Fresno, CA? The most popular types of Asic Rtl Design Engineer jobs in Fresno, CA are:
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Entry Level Asic Rtl Design Engineer jobs near you
Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Fresno, CA as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $149,131 per year, or $71.7 per hour.

AI Research Engineer, Pre-Training

Hudson River Trading

London, CA • On-site

Full-time

Re-posted 10 days ago

Job description

Hudson River Trading (HRT) is seeking an AI Research Engineer (Pre-training) to join the HAIL team. HAIL (HRT AI Labs) is the team at HRT responsible for developing and maintaining our most powerful models, which are used by our trading teams to drive a significant fraction of our trading. We are building and deploying "foundation models for markets", that ingest and train on vast amounts of market and "alternative" data (such as language) to make predictions about future market state.

As a pre-training research engineer on HAIL, you will have a general mandate to improve all aspects of large-scale model training, including but not limited to kernel development, training data loading, parallelism, networking, and fault-tolerance. You will work closely with our researchers to co-design and improve our models, and shape the research agenda.

We have multiple large, modern, and rapidly growing GPU clusters, and we maintain a very high GPU-to-researcher ratio. We are simultaneously pursuing multiple strategies and developing many model types with different purposes, and we are strongly incentivized to squeeze as much as we can out of our systems. Your work will be directly, clearly, and highly impactful on the business, and it will be challenging: this is a field with no easy or obvious solutions.

Qualifications

  • Strong engineering skills, especially any of: CUDA/Triton/Pallas/CuTe DSL kernel development, lower-level PyTorch/JAX/XLA development, CUDA Graphs, FPGA/ASIC experience
  • Must have two or more years work experience building deep learning systems, for any domain: robotics, biology, chemistry, physics, audio, video, recommendations, etc.
  • Experience translating methods between areas of application is highly valued
  • LLM experience is valuable, but not necessary
  • Finance experience is not required

The estimated base salary range for this position is 250,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

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