Entry Level Asic Rtl Design Engineer Jobs in Fresno, CA

Job Description
Job #215247
Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ.
BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE)
At least 3 year experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs.
Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
Proficiency in VHDL and FPGA design/debug Xilinx FPGA / Vivado.
Excellent Analytical/Debug skills.
Good verbal, written, and presentation skills.
US Citizenship required.
VHDL Experience is required for all candidates to be considered.
Looking for mid-senior level folks
Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
Big Plus
Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
Mentor EDA CDC/Lint/AC/RDC
POSITION RESPONSIBILITIES
The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security.
Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE)
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA).
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet).
PHYSICAL REQUIREMENTS (if noted by client in their req):
REQUIRED EDUCATION
Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.

• Education MUST be accredited**

WORK HOURS
Full-Time
Monday-Friday 08:00am-05:00pm
ADDITIONAL
Active secret clearance required.
ADDITIONAL INFORMATION

• Applicants responding to this position will be subject to a government security investigation and must meet eligibility requirements by currently possessing the ability to view classified government information.
• Employment will be contingent on clearing a drug screen and background check. Both must clear prior to start date.
• Candidates responding to this posting must currently possess the eligibility to work in the United States. No third parties please.

For more information, please apply or contact:
Robert Davis 800.927.9318 x305
rdavis@chiptonross.com
Chipton-Ross provides equal employment opportunities to all employees and applicants for employment without regard to race, color, creed, religion, national origin, sex (including pregnancy), age, disability, sexual orientation, gender identity and/or expression, protected veteran status, genetic information, or any other characteristic protected by Federal, State or local law. This policy governs all areas of employment at Chipton-Ross, including recruiting, hiring, training, assignment, promotions, compensation, benefits, discipline, and terminations.