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Asic Director Jobs (NOW HIRING)

Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project ...

ASIC Program Manager (AI Hardware) Drive the programs that bring silicon to life At BrainChip, w ... High visibility and direct impact on product delivery Details * 6-month contract * Hybrid in Laguna ...

Direct experience with AI-driven development such as coding agents and Agentic workflows. Ability ... A good understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis.

Develop simulation models, test plans, direct and random tests, code or functional coverage, multi ... Experience with ASIC design and verification processes, debugging, methodology, and tools.

Develop simulation models, test plans, direct and random tests, code or functional coverage, multi ... Experience with ASIC design and verification processes, debugging, methodology, and tools.

ASIC DFT Engineer

Fort Collins, CO ยท On-site

$108K - $172K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our Fort Collins ... The role could also involve direct interaction with external customers. It is expected that you can ...

ASIC DFT Engineer

Fort Collins, CO ยท On-site

$108K - $172K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourFort Collins ... The role could also involve direct interaction with external customers. It is expected that you can ...

ASIC Design Verification Engineer

San Jose, CA ยท On-site

$152K - $219K/yr

Develop simulation models, test plans, direct and random tests, code or functional coverage, multi ... Experience with ASIC design and verification processes, debugging, methodology, and tools.

ASIC Design Verification Engineer

San Jose, CA ยท On-site

$152K - $219K/yr

Develop simulation models, test plans, direct and random tests, code or functional coverage, multi ... Experience with ASIC design and verification processes, debugging, methodology, and tools.

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Asic Director information

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$26K

$131.5K

$218.5K

How much do asic director jobs pay per year?

As of Jun 6, 2026, the average yearly pay for asic director in the United States is $131,502.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,500.00 and $171,000.00 per year, depending on experience, location, and employer.

What are ASIC Directors?

ASIC Directors are senior executives responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They lead teams of engineers, manage project timelines and budgets, and ensure that ASIC products meet technical and business requirements. Additionally, ASIC Directors collaborate with other departments, oversee research and development efforts, and contribute to the strategic direction of semiconductor projects in their organization.

What is the difference between Asic Director vs Asic Engineer?

AspectAsic DirectorAsic Engineer
CredentialsTypically requires a Bachelor's or Master's in Electrical Engineering or Computer Engineering; leadership experienceRequires a Bachelor's or Master's in Electrical Engineering or Computer Engineering; technical expertise
Work EnvironmentLeadership roles overseeing teams, project management, strategic planningDesign, develop, and test ASIC chips; hands-on technical work
Industry UsageUsed in companies designing complex integrated circuits, often in senior or managerial contextsCommonly employed in semiconductor companies, focusing on chip design and verification

The main difference between an Asic Director and an Asic Engineer lies in their responsibilities and experience level. The Asic Director oversees teams and strategic projects, requiring leadership skills and experience, while the Asic Engineer focuses on technical design and development of ASIC chips. Both roles require similar educational backgrounds, but their scope and focus differ significantly.

What are the typical collaboration points between an ASIC Director and cross-functional teams during a project lifecycle?

An ASIC Director regularly collaborates with cross-functional teams including system architects, software engineers, hardware verification teams, and product managers. This collaboration is essential during the project lifecycle to ensure design specifications meet product requirements, timelines are aligned, and any technical challenges are addressed quickly. The ASIC Director often leads design reviews, coordinates integration testing, and communicates project status to both engineering and executive stakeholders. Effective cross-team communication helps streamline development and ensures successful delivery of complex ASIC projects.

What are the key skills and qualifications needed to thrive as an ASIC Director, and why are they important?

To thrive as an ASIC Director, you need deep expertise in digital and analog integrated circuit design, project management, and a solid background in electrical engineering or a related field, often supported by an advanced degree. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of semiconductor manufacturing processes, is essential. Strong leadership, strategic thinking, and effective communication skills set top candidates apart by enabling them to drive large teams and coordinate cross-functional development efforts. These abilities are critical for ensuring successful product delivery, innovation, and alignment with business goals in a highly competitive industry.
More about Asic Director jobs
What cities are hiring for Asic Director jobs? Cities with the most Asic Director job openings:
What are the most commonly searched types of Asic jobs? The most popular types of Asic jobs are:
What states have the most Asic Director jobs? States with the most job openings for Asic Director jobs include:
Infographic showing various Asic Director job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 83% Full Time, 13% Part Time, 1% Temporary, and 2% Contract. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $131,502 per year, or $63.2 per hour.
Senior Manager, ASIC Design

Senior Manager, ASIC Design

Marvell

Santa Clara, CA โ€ข On-site

Full-time

Life, Retirement

Posted 19 days ago


Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

What You Can Expect

We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals.

This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.

What We're Looking For

  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

  • 8+ years of ASIC/SOC digital design experience

  • 3+ years of people management experience

  • Excellent leadership, communication, team building and stakeholder management skills

  • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints

  • Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies

  • Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies

  • Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc

  • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)

  • Proficiency with front end development tools/methodologies, and scripting for automation and flow integration

Expected Base Pay Range (USD)

161,600 - 239,210, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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