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Asic Design Engineer Jobs in Oregon (NOW HIRING)

K2 Space

Senior FPGA Prototyping Engineer

OR · On-site +1

$120K - $225K/yr

Collaborate closely with ASIC Design, Verification, Firmware, Software, Systems, and DFT teams to ... Qualifications * BS or MS in Electrical Engineering, Computer Engineering, or related field. * 5+ ...

Intel

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $200K/yr

The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...

Rambus

Hardware Design Engineer

Hillsboro, OR · On-site

$106K - $198K/yr

In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $287K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $287K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Intel

DFT Application Engineer

Hillsboro, OR · On-site

Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Experience providing technical direction to engineering teams and customer support * Customer ...

Nvidia

CPU Design Methodology Engineer

OR · On-site +1

The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...

Nvidia

CPU Design Methodology Engineer

Hillsboro, OR

The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...

Nvidia

CPU Design Methodology Engineer

Hillsboro, OR

The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...

Intel

Memory Circuit Design Engineer

Hillsboro, OR · On-site

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Knowledge of the CMOS ASIC design flow. Job Type:Experienced Hire Shift:Shift 1 (United States of ...

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All JobsAsic Design Engineer JobsAsic Design Engineer Jobs in Oregon

Asic Design Engineer information

See Oregon salary details

$99.4K

$158.8K

$213.6K

How much do asic design engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for asic design engineer in Oregon is $158,800.00, according to ZipRecruiter salary data. Most workers in this role earn between $139,000.00 and $190,300.00 per year, depending on experience, location, and employer.

What is an ASIC design engineer?

ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.

What does an ASIC design engineer do?

An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.

What are the key skills and qualifications needed to thrive as an ASIC design engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.

What are some common challenges faced by ASIC design engineers during the design and verification phases?

ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.

What is the difference between Asic Design Engineer vs FPGA Design Engineer?

AspectAsic Design EngineerFPGA Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning custom chips for manufacturingDeveloping programmable logic designs for prototyping and deployment
Industry UsageSemiconductor companies, consumer electronics, automotivePrototyping, testing, and specialized hardware applications

Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.

Are ASIC design engineers in demand?

ASIC design engineers are in high demand due to the growth of semiconductor technology, consumer electronics, and data centers. Skills in hardware description languages like VHDL or Verilog, along with experience in FPGA and ASIC development, increase employability in this field.

How much does an ASIC design engineer make?

The average salary for an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $180,000.
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Asic Design Engineer jobs near you
Infographic showing various Asic Design Engineer job openings in Oregon as of September 2026, with employment types broken down into 1% Internship, 83% Full Time, 12% Part Time, and 4% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $158,800 per year, or $76.3 per hour.

Senior FPGA Prototyping Engineer

OR • On-site, Remote

K2 Space
Guided Missile and Space Vehicle Manufacturing • 11 - 50 employees
Learn more about K2 Spaceexternal

$120K - $225K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 3 days ago

Job description

The Role

We are seeking a Senior FPGA & Silicon Bring-up Engineer to accelerate the development of next-generation communications ASICs. You will own FPGA prototyping, firmware enablement, first-silicon bring-up, and hardware validation, serving as the bridge between ASIC design, firmware, software, and system integration. This role spans the entire silicon lifecycle from pre-silicon FPGA platforms that enable early hardware/software integration to post-silicon debug, interface validation, and automated test infrastructure.

Responsibilities

  • Develop FPGA-based prototypes to enable early ASIC integration, firmware development, and system validation.
  • Build hardware platforms that allow software and firmware teams to develop before first silicon.
  • Support first-silicon bring-up, debug, and functional validation.
  • Develop automated validation infrastructure for silicon characterization and regression testing.
  • Configure and validate digital interfaces including high-speed Ethernet SerDes, SPI, UART, GPIO, and other peripheral interfaces.
  • Develop FPGA-based traffic generators, protocol checkers, and test applications for interface validation.
  • Debug issues spanning RTL, firmware, software, FPGA prototypes, and silicon using simulation and laboratory instrumentation.
  • Collaborate closely with ASIC Design, Verification, Firmware, Software, Systems, and DFT teams to accelerate product development.

Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of FPGA development experience using Verilog/SystemVerilog and AMD/Xilinx FPGA tools.
  • Strong understanding of ASIC development and digital system architecture.
  • Experience with FPGA prototyping for ASIC development.
  • Experience with firmware/software enablement and hardware bring-up.
  • Strong hardware debugging skills using JTAG, oscilloscopes, logic analyzers, and protocol analyzers.
  • Proficiency with Python and scripting for automation and test infrastructure.

Nice to Have

  • Experience with networking, communications, or satellite systems.
  • Experience with embedded processors (ARM or RISC-V).
  • Experience working with hard real-time embedded systems (bare-metal or RTOS).
  • Experience validating high-speed digital interfaces, including Ethernet and SerDes protocols, SPI, and UART.
  • Experience with silicon bring-up using JTAG, logic analyzers, and oscilloscopes.

Compensation and Benefits:

  • Base salary range for this role is $120,000 - $225,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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