... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
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Apply Early
ASIC Design Engineer
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Apply Early
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
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Apply Early
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Apply Early
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC Design Engineer
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Quick apply
Apply Early
ASIC Design Engineer
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Apply Early
ASIC Design Engineer
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Quick apply
Apply Early
ASIC Design Engineer
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Apply Early
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
Power Engineer (RTL Design)
Austin, TX · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. Strong background in RTL design and verification principles. Demonstrable experience with power profiling tools such as PPRTL or ...
Power Engineer (RTL Design)
Austin, TX · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. Strong background in RTL design and verification principles. Demonstrable experience with power profiling tools such as PPRTL or ...
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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Apply Early
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Apply Early
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Staff ASIC Design Engineer
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
Staff ASIC Design Engineer
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC RTL Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do asic rtl design engineer jobs pay per year?
What is an ASIC RTL Design Engineer job?
An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.
What are the typical daily responsibilities of an ASIC RTL Design Engineer?
As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.
What are the key skills and qualifications needed to thrive in the Asic Rtl Design Engineer position, and why are they important?
To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.

Apple rating
8.1
Based on 667 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 0 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976