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60 Intel Physical Design Engineer Jobs Hiring Near You

Intel

Silicon Packaging Design Engineer

Phoenix, AZ · On-site

$135K/yr

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... Key Responsibilities: - Design and implement physical layout and routing of silicon interposers and ...

Intel

Silicon Packaging Design Engineer

Hillsboro, OR · On-site

$148K/yr

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... Key Responsibilities: - Design and implement physical layout and routing of silicon interposers and ...

Intel

Design Engineer - AI SoC Development

Folsom, CA · On-site

Join Intel's AI Revolution Intel's AI SoC organization develops cutting-edge products powering a ... design integrity for physical implementation. Working closely with verification teams, you'll ...

Intel

Design Engineer - AI SoC Development

Austin, TX · On-site

Join Intel's AI Revolution Intel's AI SoC organization develops cutting-edge products powering a ... design integrity for physical implementation. Working closely with verification teams, you'll ...

Intel

SoC Design Engineer

Austin, TX · On-site

$122K - $232K/yr

Your contributions will directly impact the success of Intel's products by enabling power-efficient ... Experience with tools and strategies for RTL design, SoC integration, and physical implementation ...

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Intel is a technology company that values innovation, collaboration, and diversity, fostering a culture that encourages employees to think creatively and push boundaries. The company's structure is organized into various teams, including research and development, engineering, and manufacturing, with a focus on delivering cutting-edge technology solutions. Working at Intel may appeal to candidates who are passionate about advancing technology and contributing to the development of products that transform people's lives, with opportunities to work on complex projects and collaborate with a global team of experts.

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Most people find out their schedule less than four weeks ahead of time.
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Infographic showing various Physical Design Engineer job openings at Intel in the United States as of July 2026, with employment types broken down into 98% Full Time, 1% Part Time, and 1% Nights. Highlights an 97% Physical, 2% Hybrid, and 1% Remote job distribution.
Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

Intel

Hillsboro, OR • On-site

Full-time

Medical, Retirement, PTO

Posted 25 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 145 frontline employees who took The Breakroom Quiz

10th of 141 rated electronics manufacturers

Job description

Job Details:Job Description: 

About the Role

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.

In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.

What You'll Do

Key responsibilities will include but not limited to:

  • Developing layout design methodology for testchip development in next generation process nodes
  • Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
  • Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
  • Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
  • Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
  • Working with tool/flow owners and vendors for ongoing tool/methodology improvement

Behavioral traits that we are looking for:

  • Exhibiting strong interest in Layout design in advanced technology nodes.
  • Strong verbal and written communication skills
  • Ability to work well both autonomously and in an intensive, cooperative team environment
  • Coordinate between different stakeholders for testchip to arrive at execution commit for testchip
  • Motivation to continuously learn and drive to push improved layout productivity and efficiency

Why Join Us

  • Work on cutting-edge semiconductor technologies that shape the future of computing
  • Collaborate with industry-leading experts across design and manufacturing
  • Opportunities for career growth and technical leadership
  • Contribute to innovations that impact global technology at scale
  • Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life

See Intel Benefitsfor more details.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel's immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information

Minimum Qualifications and Experience:


Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:

  • Experience with physical/layout design in advance technology nodes
  • In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
  • Design rules and layout constraints in advanced semiconductor processes
  • Experience with floorplanning, hierarchical design integration, and layout verification/debug

Preferred Qualifications and Experience:

  • Experience in Definition of Testchip/Product design from Concept to Execution Commit
  • Experience in working with Foundry teams on negotiating features to exercise in design
  • Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
  • Previous related work experience in a semiconductor foundry preferred
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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