... Analog/Mixed Signal Application Engineer specializing in Analog Mixed-Signal Design provides ... Collaborate with internal Intel teams and external stakeholders including foundry customers' design ...

60 Intel Analog Design Engineer Jobs Hiring Near You
... Analog/Mixed Signal Application Engineer specializing in Analog Mixed-Signal Design provides ... Collaborate with internal Intel teams and external stakeholders including foundry customers' design ...
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Director-Analog Design & Infrastructure Design Automation
Hillsboro, OR · On-site
$180.80K/yr
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Director-Analog Design & Infrastructure Design Automation
Hillsboro, OR · On-site
$180.80K/yr
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Director-Analog Design & Infrastructure Design Automation
Santa Clara, CA · On-site
$195K/yr
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Director-Analog Design & Infrastructure Design Automation
Santa Clara, CA · On-site
$195K/yr
Lead and mentor DA and infrastructure engineers. * Serve as the primary interface between analog ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
Mixed Signal Logic Design Engineer
$122.44K - $232.19K/yr
Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... This position is not eligible for an intel immigration sponsorship. Preferred Qualifications:
New
Mixed Signal Logic Design Engineer
$122.44K - $232.19K/yr
Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... This position is not eligible for an intel immigration sponsorship. Preferred Qualifications:
New
Mixed Signal Logic Design Engineer
$122.44K - $232.19K/yr
Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... This position is not eligible for an intel immigration sponsorship. Preferred Qualifications:
New
Mixed Signal Logic Design Engineer
$122.44K - $232.19K/yr
Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... This position is not eligible for an intel immigration sponsorship. Preferred Qualifications:
New
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122.44K - $232.19K/yr
Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... This position is not eligible for an intel immigration sponsorship. Preferred Qualifications:
New
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122.44K - $232.19K/yr
Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... This position is not eligible for an intel immigration sponsorship. Preferred Qualifications:
New
Memory Circuit Design Engineer
$122.44K - $232.19K/yr
At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the ... Experience with EDA tools used for analog, digital and mixed-signal circuit design. * Post-Si ...
Memory Circuit Design Engineer
$122.44K - $232.19K/yr
At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the ... Experience with EDA tools used for analog, digital and mixed-signal circuit design. * Post-Si ...
Memory Circuit Design Engineer
Hillsboro, OR · On-site
$122.44K - $232.19K/yr
At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the ... Experience with EDA tools used for analog, digital and mixed-signal circuit design. * Post-Si ...
Memory Circuit Design Engineer
Hillsboro, OR · On-site
$122.44K - $232.19K/yr
At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the ... Experience with EDA tools used for analog, digital and mixed-signal circuit design. * Post-Si ...
Memory Circuit Design Engineer
Hillsboro, OR · On-site
$122.44K - $232.19K/yr
At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the ... Experience with EDA tools used for analog, digital and mixed-signal circuit design. * Post-Si ...
Memory Circuit Design Engineer
Hillsboro, OR · On-site
$122.44K - $232.19K/yr
At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the ... Experience with EDA tools used for analog, digital and mixed-signal circuit design. * Post-Si ...
Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...
Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...
Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...
Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...
Silicon Packaging Design Engineer
Phoenix, AZ · On-site
$135K/yr
Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...
Silicon Packaging Design Engineer
Phoenix, AZ · On-site
$135K/yr
Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...
Senior Design Verification Engineer- Mixed Signal IP
Santa Clara, CA · On-site
$164.47K - $311.89K/yr
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... Collaborates with digital and analog architects, RTL developers, and physical design teams to ...
Senior Design Verification Engineer- Mixed Signal IP
Santa Clara, CA · On-site
$164.47K - $311.89K/yr
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... Collaborates with digital and analog architects, RTL developers, and physical design teams to ...
Senior Design Verification Engineer- Mixed Signal IP
$164.47K - $311.89K/yr
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... Collaborates with digital and analog architects, RTL developers, and physical design teams to ...
Senior Design Verification Engineer- Mixed Signal IP
$164.47K - $311.89K/yr
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... Collaborates with digital and analog architects, RTL developers, and physical design teams to ...
SoC Design Engineer
$122.44K - $232.19K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge System on Chip (SoC) designs. This role offers an exciting opportunity ...
SoC Design Engineer
$122.44K - $232.19K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge System on Chip (SoC) designs. This role offers an exciting opportunity ...
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... As a CPU Logic Design Engineer, you will play a pivotal role in designing and developing the logic ...
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... As a CPU Logic Design Engineer, you will play a pivotal role in designing and developing the logic ...
SoC Design Engineer
Austin, TX · On-site
$122.44K - $232.19K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge System on Chip (SoC) designs. This role offers an exciting opportunity ...
SoC Design Engineer
Austin, TX · On-site
$122.44K - $232.19K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge System on Chip (SoC) designs. This role offers an exciting opportunity ...
Intel Jobs Information
What does an Analog Design Engineer do?
What are the key skills and qualifications needed to thrive in the Analog Design Engineer position, and why are they important?
What does a typical workday look like for an Analog Design Engineer?
What is it like to work at Intel?
Do workers at Intel get paid breaks?
86% of people say they get paid breaks.
Based on data from 74 people who took the Breakroom Quiz between May 2025 and April 2026.
Does Intel pay people when they’re sick?
87% of people say they would get paid if they were sick but scheduled to work.
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34% of people say they have to use vacation days when they’re out sick.
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96% of people say they get paid time off.
Based on data from 68 people who took the Breakroom Quiz between May 2025 and April 2026.
How far ahead of time do people find out their work schedule?
- 60% of people with changing schedules find out their shifts one week or less ahead of time.
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Full-time
Medical, Retirement, PTO
Posted 17 days ago
Intel rating
8.8
Based on 143 frontline employees who took The Breakroom Quiz
9th of 137 rated electronics manufacturers
Job description
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
The Aerospace, Defense & Government (ADG) Senior Analog/Mixed Signal Application Engineer specializing in Analog Mixed-Signal Design provides critical technical support to Intel Foundry Services customers on PDKs, design methodologies, and implementation flows. This role ensures successful customer tape-outs through expert guidance on analog/mixed-signal design challenges while driving quality improvements in design kits and documentation.
Key Responsibilities
Customer Technical Support & Collaboration
- Provide comprehensive tool/flow/methodology support to address customer analog mixed-signal design issues and challenges, ensuring successful tape-outs and maximum customer satisfaction
- Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on AMS design and layout issue resolution
- Support customers through complex analog design challenges and advanced process technology adoption
Technical Content Development & Training
- Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
- Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
- Develop best practice guidelines for analog mixed-signal design implementation across advanced CMOS processes
Analog Design Methodology Leadership
- Provide technical direction on custom/analog mixed-signal design and layout methodologies
- Support analog tool flows including schematic entry, analog/RF simulation, extraction, post-layout simulation, and reliability validation
- Drive methodology improvements to streamline customer design workflows and enhance design productivity
Core Competencies
- Self-driven and results-oriented with capability to effectively manage multiple tasks
- Strong analytical problem-solving skills for complex analog design challenges
- Effective communication skills with experience in collaboration, active listening, and providing constructive feedback
Qualifications:
Minimum Qualifications
- US Citizenship required
- Ability to obtain US Government Security Clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field of study
- 5+ years of experience with advanced CMOS processes (16nm and below)
- 4+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, shell scripting)
- Hands-on experience in Design Implementation and methodology, specifically in Custom/Analog Mixed-Signal design/layout
Preferred Qualifications
- Active US Government Security Clearance with a minimum of Secret level.
- Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
- Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work.
- Hands-on experience with analog tool and flows: Schematic entry, analog/RF simulation, extraction, post layout simulation, reliability validation.
- Hands on experience with custom layout of analog blocks and Layout migration b/w different advanced FINFET tech nodes.
- Experience in design of RF/analog/mixed-signal blocks: Low-noise amplifiers, filters, mixers, VCO, PLL, clock recovery, clock distribution, ADC/DAC, etc.
- Customer facing experience.
- Experience in SOTA Process technology (7nm and below) and PDK based technology evaluation.
- Experience with thermal analysis at the block and die level using tools such as Ansys Icepak and/or Cadence Celsius
What We Offer
- Opportunity to work with cutting-edge analog mixed-signal technologies for aerospace, defense, and government applications
- Direct customer engagement and technical leadership in advanced semiconductor design
- Access to Intel's most advanced foundry technologies and comprehensive analog design tool suites
- Competitive compensation
- Professional development in analog design methodologies and foundry services
- Direct impact on national security through advanced analog semiconductor solutions
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968